Patents by Inventor Yung Lin
Yung Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12389507Abstract: A controller for controlling a light source module including a first LED string and a second LED string includes a power input terminal operable for receiving electric power from a boost converter, a power output terminal operable for providing electric power to the light source module through a buck converter, a first input terminal operable for receiving a first pulse width modulation (PWM) signal, a second input terminal operable for receiving a second PWM signal, and a width monitoring terminal operable for receiving a width monitoring signal indicating a duration of a first state of the first PWM signal and a duration of a first state of the second PWM signal. The controller is operable for turning off the light source module if the width monitoring signal is greater than a width threshold signal.Type: GrantFiled: September 8, 2023Date of Patent: August 12, 2025Assignee: O2Micro Inc.Inventors: Naoyuki Fujita, Rong Hu, Yung-Lin Lin
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Publication number: 20250246215Abstract: A semiconductor structure includes a memory cell connected to a signal line, a first voltage line for receiving a power supply voltage, and a second voltage line for receiving an electric ground voltage, a logic cell configured to provide logic function to the memory cell, a transition region extending from a first boundary of the memory cell to a second boundary of the logic cell, and an interconnect structure disposed over the memory cell and the logic cell. The interconnect structure includes the signal line, the first voltage line, and the second voltage line located in a same metal line layer of the interconnect structure. The signal line extends from inside the second boundary of the logic cell and into the first boundary of the memory cell. The transition region includes one or more functional transistors electrically coupled to the memory cell.Type: ApplicationFiled: January 30, 2024Publication date: July 31, 2025Inventors: Chia He Chung, Chih-Yung Lin, Kuo-Hua Pan, Chih-Hung Hsieh, Dian-Sheng Yu
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Patent number: 12370661Abstract: A hammer tacker is provided, wherein the hammer tacker includes: a main body integrally made of plastic and including two side walls and a top wall, each side wall including an ear portion which includes a stop point, a first position and a second position between two ends of each side wall and the stop point, each side wall being gradually thicker from the first position to the stop point, from the second position to the stop point, and from the top wall to the stop point; and a striking mechanism rotatably connected to the two side walls and swingable to abut against the stop point, including a magazine and a striking member, the magazine being disposed between the two side walls and movable relative to the main body, movably located above the magazine, and being configured to strike a staple out from the magazine.Type: GrantFiled: August 6, 2024Date of Patent: July 29, 2025Assignee: APEX MFG. CO., LTD.Inventor: Chih-Yung Lin
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Patent number: 12376209Abstract: A controller for controlling a light source module including a first LED array and a second LED array includes a first driving terminal and a second driving terminal. The controller is operable for turning on a switch between a power converter and the first LED array by the first driving terminal to deliver electric power from the power converter to the first LED array in a first sequence of discrete time slots, and for turning on a second switch between the power converter and the second LED array by the second driving terminal to deliver electric power from the power converter to the second LED array in a second sequence of discrete time slots, where the first sequence of discrete time slots and the second sequence of discrete time slots are mutually exclusive.Type: GrantFiled: January 25, 2024Date of Patent: July 29, 2025Assignee: O2Micro Inc.Inventors: Rong Hu, Yung-Lin Lin, Naoyuki Fujita
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Patent number: 12349920Abstract: A tourniquet includes an elastic band including uneven top and bottom surface. The uneven surface includes rows of a plurality of spaced first uneven zones and rows of a plurality of spaced second uneven zones. The first uneven zone is disposed between two adjacent ones of the second uneven zone. The second uneven zone is disposed between two adjacent ones of the first uneven zone. The first and second uneven zones are concave rectangular. Each uneven zone includes two raised, opposite inclined edges and the other two raised, opposite inclined edges. A ridge is formed between two adjacent inclined edges of different uneven zones.Type: GrantFiled: December 7, 2022Date of Patent: July 8, 2025Assignee: Wheelstone Enterprise Co., Ltd.Inventor: Yung-Lin Hsieh
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Publication number: 20250210389Abstract: In an embodiment, a system, includes: a first pressurized load port interfaced with a workstation body; a second pressurized load port interfaced with the workstation body; the workstation body maintained at a set pressure level, wherein the workstation body comprises an internal material handling system configured to move a semiconductor workpiece within the workstation body between the first and second pressurized load ports at the set pressure level; a first modular tool interfaced with the first pressurized load port, wherein the first modular tool is configured to process the semiconductor workpiece; and a second modular tool interfaced with the second pressurized load port, wherein the second modular tool is configured to inspect the semiconductor workpiece processed by the first modular tool.Type: ApplicationFiled: March 11, 2025Publication date: June 26, 2025Inventors: Chun-Jung HUANG, Yung-Lin HSU, Kuang Huan HSU, Jeff CHEN, Steven HUANG, Yueh-Lun YANG
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Patent number: 12324199Abstract: The present disclosure describes a semiconductor device with a fill structure. The semiconductor structure includes first and second fin structures on a substrate, an isolation region on the substrate and between the first and second fin structures, a first gate structure disposed on the first fin structure and the isolation region, a second gate structure disposed on the second fin structure and the isolation region, and the fill structure on the isolation region and between the first and second gate structures. The fill structure includes a dielectric structure between the first and second gate structures and an air gap enclosed by the dielectric structure. The air gap is below top surfaces of the first and second fin structures.Type: GrantFiled: March 4, 2024Date of Patent: June 3, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsiu-Yung Lin, Yen Chuang, Min-Hao Hong
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Publication number: 20250170813Abstract: A composite film, a decorative film and a method of decorating a target substrate are provided. The composite film includes a substrate and a transfer layer disposed on a surface of the substrate. The transfer layer has a loss factor (tan ?) in a range between 0.015 and 0.1. The composite film is configured to prepare a laminated thin film, a cold pressed film and a hot pressed film. By controlling property of the transfer layer, material cost of the processes for decorating the target substrate and procedure of waste treatment can be decreased.Type: ApplicationFiled: November 28, 2024Publication date: May 29, 2025Inventors: Ming Chieh KUO, Yin Yung LIN, Chao Wei LIU, Yu Chang HSU, Chien Liang KUO
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Publication number: 20250169163Abstract: Examples of an integrated circuit with a capacitor structure and a method for forming the integrated circuit are provided herein. In some examples, an integrated circuit device includes a substrate and a trench isolation material disposed on the substrate. An isolation structure is disposed on the trench isolation material. A first electrode disposed on the isolation structure, and a second electrode disposed on the isolation structure. A capacitor dielectric is disposed on the isolation structure between the first electrode and the second electrode. In some such examples, the isolation structure includes a first hard mask disposed on the trench isolation material, a dielectric disposed on the first hard mask, and a second hard mask disposed on the dielectric.Type: ApplicationFiled: January 17, 2025Publication date: May 22, 2025Inventors: Hsiao-Han Liu, Hoppy Lee, Chung-Yu Chiang, Po-Nien Chen, Chih-Yung Lin
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Patent number: 12272580Abstract: In an embodiment, a system, includes: a first pressurized load port interfaced with a workstation body; a second pressurized load port interfaced with the workstation body; the workstation body maintained at a set pressure level, wherein the workstation body comprises an internal material handling system configured to move a semiconductor workpiece within the workstation body between the first and second pressurized load ports at the set pressure level; a first modular tool interfaced with the first pressurized load port, wherein the first modular tool is configured to process the semiconductor workpiece; and a second modular tool interfaced with the second pressurized load port, wherein the second modular tool is configured to inspect the semiconductor workpiece processed by the first modular tool.Type: GrantFiled: January 3, 2024Date of Patent: April 8, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Jung Huang, Yung-Lin Hsu, Kuang Huan Hsu, Jeff Chen, Steven Huang, Yueh-Lun Yang
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Publication number: 20250098060Abstract: A component carrier includes a stack with at least one electrically conductive layer structure and/or at least one electrically insulating layer structure, and a solder resist structure on at least one of two opposing main surfaces of the stack. The solder resist structure includes at least two different kinds of solder resist provided on one of said main surfaces.Type: ApplicationFiled: September 20, 2023Publication date: March 20, 2025Inventors: Lei Tang, Yung-lin Chia
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Patent number: 12255105Abstract: A semiconductor device includes a substrate having a first region and a second region, a first transistor in the first region, a second transistor in the first region, and a third transistor in the second region. The first transistor includes a first channel layer and a first gate dielectric layer on the first channel layer. The second transistor includes a second channel layer and a second gate dielectric layer on the second channel layer. The second gate dielectric layer is thicker than the first gate dielectric layer. The third transistor includes a third channel layer and a third gate dielectric layer on the third channel layer. The third gate dielectric layer is thicker than the second gate dielectric layer.Type: GrantFiled: June 30, 2021Date of Patent: March 18, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Pei-Hsun Wu, Ming-Hung Han, Po-Nien Chen, Chih-Yung Lin
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Publication number: 20250089139Abstract: A controller for controlling a light source module including a first LED string and a second LED string includes a power input terminal operable for receiving electric power from a boost converter, a power output terminal operable for providing electric power to the light source module through a buck converter, a first input terminal operable for receiving a first pulse width modulation (PWM) signal, a second input terminal operable for receiving a second PWM signal, and a width monitoring terminal operable for receiving a width monitoring signal indicating a duration of a first state of the first PWM signal and a duration of a first state of the second PWM signal. The controller is operable for turning off the light source module if the width monitoring signal is greater than a width threshold signal.Type: ApplicationFiled: September 8, 2023Publication date: March 13, 2025Inventors: Naoyuki FUJITA, Rong HU, Yung-Lin LIN
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Patent number: 12248343Abstract: Aspects of the embodiments are directed to a rack server that includes a rack server chassis; a plurality of backplane printed circuit boards (PCBs) coupled to the rack server chassis, each backplane PCB comprising a plurality of cantilevered beams, each cantilevered beam of the plurality of cantilevered beams comprising a receiver slot to receive a server element; and a serial attached small computer serial interface (SAS) expander circuit element residing on each backplane PCB, the SAS expander circuit element electrically connected to the receiver slot of each cantilevered beam of the plurality of cantilevered beams. The rack server comprises a 5 RU height.Type: GrantFiled: February 28, 2023Date of Patent: March 11, 2025Assignee: Hyve Solutions CorporationInventors: Jayarama Narayan Shenoy, Chiaming Liu, Chihwei Lee, John Will Wallerich, Robert Michael Kinstle, III, ChungTa Huang, Yung-Ning Mo, Chia-Yung Lin, Hsuanju Shen
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Patent number: 12243871Abstract: Examples of an integrated circuit with a capacitor structure and a method for forming the integrated circuit are provided herein. In some examples, an integrated circuit device includes a substrate and a trench isolation material disposed on the substrate. An isolation structure is disposed on the trench isolation material. A first electrode disposed on the isolation structure, and a second electrode disposed on the isolation structure. A capacitor dielectric is disposed on the isolation structure between the first electrode and the second electrode. In some such examples, the isolation structure includes a first hard mask disposed on the trench isolation material, a dielectric disposed on the first hard mask, and a second hard mask disposed on the dielectric.Type: GrantFiled: February 20, 2023Date of Patent: March 4, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hsiao-Han Liu, Hoppy Lee, Chung-Yu Chiang, Po-Nien Chen, Chih-Yung Lin
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Publication number: 20250057876Abstract: Disclosed herein is a method for treating and/or preventing a lymphangiogenesis-associated disease in a subject, including administering to the subject a therapeutically effective amount of a dihydrolipoic acid (DHLA)-coated gold nanocluster about 0.1 to 10 nm in diameter. Also disclosed is a method for promoting lymphangiogenesis in a subject, including administering to the subject an effective amount of said DHLA-coated gold nanocluster.Type: ApplicationFiled: August 18, 2023Publication date: February 20, 2025Inventors: Hung-I YEH, Yih-Jer WU, Shih-Wei WANG, Ching-Hu CHUNG, Cheng-Yung LIN, Wen-Hsiung CHAN, Kuan-Jung LI, Hong-Shong CHANG
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Publication number: 20250033091Abstract: A brush wetting and cleaning system or tool including a brush wetting and cleaning housing. A wetting nozzle in fluid communication with a cavity in the brush wetting and cleaning housing. The wetting nozzle is configured to, in operation, wet a brush of a brush head inserted into the cavity of the brush wetting and cleaning housing. A spray nozzle in fluid communication with the cavity in the brush wetting and cleaning housing. The spray nozzle is configured to, in operation, clean the brush of the brush head inserted into the cavity of the brush wetting and cleaning housing. In a method of utilizing the brush wetting and cleaning system or tool, the brush of the brush head is wetted and cleaned between cleaning successive wafers or workpieces.Type: ApplicationFiled: July 28, 2023Publication date: January 30, 2025Inventors: Shao-Yen KU, Ying-Chuan SU, Hao Yu WANG, Huan-Yung LIN
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Publication number: 20250034723Abstract: The present invention provides a gas generator, comprising a water tank and an electrolysis device. The water tank has a first hollow portion for containing electrolyzed water. The electrolysis device is disposed inside the first hollow portion of the water tank for electrolyzing the electrolyzed water to generate a hydrogen-oxygen mixed gas. When the electrolysis device starts to electrolyze the electrolyzed water, the first hollow portion of the water tank is filled with the electrolyzed water for standing at a full level of water. And after the electrolysis device electrolyzed the electrolyzed water, the level of water for the electrolyzed water filled into the first hollow portion of the water tank is higher than 95% of the full level of water. The gas generator of the present invention provides the design for saving space and nearly a zero gas chamber to reduce the possibility of explosions resulting from hydrogen-oxygen mixed gas.Type: ApplicationFiled: October 11, 2024Publication date: January 30, 2025Inventor: Hsin-Yung Lin
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Patent number: 12213303Abstract: The present disclosure provides a semiconductor device and a fabricating method thereof, and which includes a substrate, bit lines, bit line contacts, a gate structure, a first oxidized interface layer, and a second oxidized interface layer. The bit lines are disposed on the substrate, and the bit line contacts are disposed below the bit lines. The gate structure is disposed on the substrate, wherein each bit line and the gate structure respectively include a semiconductor layer, a conductive layer, and a covering layer stacked from bottom to top. The first oxidized interface layer is disposed between each bit line contact and the semiconductor layer of each bit line. The second oxidized interface layer is disposed within the semiconductor layer of the gate structure, wherein a topmost surface of the first oxidized interface layer is higher than a topmost surface of the second oxidized interface layer.Type: GrantFiled: April 21, 2022Date of Patent: January 28, 2025Assignee: Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Yukihiro Nagai, Lu-Yung Lin, Chia-Wei Wu, Tsun-Min Cheng, Yu Chun Lin, Zheng Guo Zhang, Sun-Hung Chen, Wu Xiang Li, Hsiao-Han Lin
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Patent number: D1065961Type: GrantFiled: March 6, 2023Date of Patent: March 11, 2025Assignee: HAN LIEN INTERNATIONAL CORP.Inventor: Hsiao-Yung Lin Joh