Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. In one embodiment, a material layer is formed over a substrate and a first hard mask (HM) feature is formed over the material layer. The HM feature includes an upper portion having a first width and a lower portion having a second width which is greater than the first width. The method also includes forming spacers along sidewalls of the first HM feature, forming second HM features over the material layer by using the spacers as a first etch mask and forming patterned features in the material layer by using the second HM features as a second etch mask.

Abstract: Directional patterning methods are disclosed herein. An exemplary method includes performing a lithography process to form a pattered hard mask layer over a wafer, wherein the patterned hard mask layer includes a hard mask feature having an associated horizontally-defined characteristic; tuning an etching process to direct etching species in a substantially horizontal direction relative to a horizontal surface of the wafer, such that the etching process horizontally removes portions of the patterned hard mask layer, thereby modifying the horizontally-defined characteristic of the hard mask feature; and forming an integrated circuit feature that corresponds with the hard mask feature having the modified horizontally-defined characteristic. Horizontally-defined characteristic can include a length, a width, a line edge roughness, a line width roughness, a line end profile, other horizontally-defined characteristics, or combinations thereof.

Abstract: A method of fabricating a semiconductor device includes forming a hard mask (HM) mandrel along a first direction over a material layer, forming a first spacer along a sidewall of the HM mandrel, forming a second spacer along a sidewall of the first spacer and forming a patterned photoresist layer having a first line opening over the HM mandrel, the first spacer and the second spacer. First portions of the HM mandrel, the first spacer and the second spacer are exposed within the first line opening. The method also includes removing the first portion of the first spacer through the first line opening to expose a first portion of the material layer and etching the exposed first portion of the material layer to form a first opening in the material layer by using the exposed first portions of the HM mandrel and the second spacer as a sub-etch-mask.

Abstract: The present disclosure relates to an integrated chip that uses a metal strap to improve performance and reduce electromigration by coupling a middle-end-of-the-line (MEOL) layer to a power rail. In some embodiments, the integrated chip has an active area with a plurality of source/drain regions. The active area contacts a MEOL structure extending in a first direction. A first metal wire extends in a second direction, which is perpendicular to the first direction, at a location overlying the MEOL structure. A metal strap extending in a first direction is arranged over the first metal wire. The metal strap is configured to connect the first metal line to a power rail (e.g., which may be held at a supply or ground voltage), which extends in the second direction. By connecting the MEOL structure to the power rail by way of a metal strap, parasitic capacitance and electromigration may be reduced.

Abstract: In some embodiments, the present disclosure relates to an integrated chip having a lower power rail continuously extending over a plurality of gate structures. A first set of connection pins straddle a first edge of the lower power rail, and a second set of connection pins straddle a second edge of the lower power rail, which is opposite the first edge. The first set of connection pins and the second set of connection pins are electrically coupled to the lower power rail. An upper power rail is over the lower power rail and is electrically coupled to the first set of connection pins and the second set of connection pins. The first set of connection pins are arranged at a first pitch and the second set of connection pins arranged with respect to the first set of connection pins at a second pitch less than the first pitch.

Abstract: Various patterning methods involved with manufacturing semiconductor device structures are disclosed herein. A method for forming a semiconductor device structure (for example, a conductive line) includes forming a first hard mask layer and a second hard mask layer over a dielectric layer. The first hard mask layer has a first opening, and the second hard mask layer has a first trench connected to the first opening. A filling layer is formed in the first opening, where the filling layer has a second opening and a third opening. The first hard mask layer and the dielectric layer are removed through the second opening and the third opening to form a second trench and a third trench in the dielectric layer. The first hard mask layer, the second hard mask layer, and the filling layer can be removed. A conductive layer is formed in the second trench and the third trench.

Abstract: Various patterning methods involved with manufacturing semiconductor devices are disclosed herein. A method for fabricating a semiconductor structure (for example, interconnects) includes forming a patterned photoresist layer over a dielectric layer. An opening (hole) is formed in the patterned photoresist layer. In some embodiments, a surrounding wall of the patterned photoresist layer defines the opening, where the surrounding wall has a generally peanut-shaped cross section. The opening in the patterned photoresist layer can be used to form an opening in the dielectric layer, which can be filled with conductive material. In some embodiments, a chemical layer is formed over the patterned photoresist layer to form a pair of spaced apart holes defined by the chemical layer, and an etching process is performed on the dielectric layer using the chemical layer as an etching mask to form a pair of spaced apart holes through the dielectric layer.

Abstract: The present disclosure relates to an integrated chip that uses a metal strap to improve performance and reduce electromigration by coupling a middle-end-of-the-line (MEOL) layer to a power rail. In some embodiments, the integrated chip has an active area with a plurality of source/drain regions. The active area contacts a MEOL structure extending in a first direction. A first metal wire extends in a second direction, which is perpendicular to the first direction, at a location overlying the MEOL structure. A metal strap extending in a first direction is arranged over the first metal wire. The metal strap is configured to connect the first metal line to a power rail (e.g., which may be held at a supply or ground voltage), which extends in the second direction. By connecting the MEOL structure to the power rail by way of a metal strap, parasitic capacitance and electromigration may be reduced.

Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming a first flowable-material (FM) layer over a substrate. A top surface of the first FM layer in a first region is higher than a top surface of the first FM layer in a second region. The method also includes forming a sacrificial plug to cover the first FM layer in the first region, forming a second FM layer over the sacrificial plug in the first region and over the first FM layer in the second region, performing a first recessing process such that the second FM layer is removed in the first region and performing a second recessing process on the second FM layer in the second region while the first FM layer is protected by the sacrificial plug in the first region.

Abstract: A method for fabricating a semiconductor device includes forming a first material layer over a substrate, forming a middle layer over the first material layer, forming a first hard mask (HM) layer over the middle layer, forming a second HM layer over the first HM layer, forming a first trench in the second HM layer that extends into the first HM layer, forming a second trench in the second HM layer, The second trench is parallel to the first trench. The method also includes forming a first hole feature in the middle layer within the first trench by using the second HM layer and the first HM layer as a mask and forming a second hole feature in the middle layer within the second trench by using the second HM layer as a mask.

Abstract: The present disclosure relates to an integrated chip having a dual power rail structure. In some embodiments, the integrated chip has a first metal interconnect layer having a lower metal wire extending in a first direction. A second metal interconnect layer has a plurality of connection pins coupled to the lower metal wire by way of a first via layer and extending over the lower metal wire in a second direction perpendicular to the first direction. A third metal interconnect layer has an upper metal wire extending over the lower metal wire and the connection pins in the first direction. The upper metal wire is coupled to the connection pins by way of a second via layer arranged over the first via layer. Connecting the connection pins to the lower and upper metal wires reduces current density in connections to the connection pins, thereby reducing electromigration and/or IR issues.

Abstract: A method of fabricating a semiconductor device includes forming a hard mask (HM) mandrel along a first direction over a material layer, forming a first spacer along a sidewall of the HM mandrel, forming a second spacer along a sidewall of the first spacer and forming a patterned photoresist layer having a first line opening over the HM mandrel, the first spacer and the second spacer. First portions of the HM mandrel, the first spacer and the second spacer are exposed within the first line opening. The method also includes removing the first portion of the first spacer through the first line opening to expose a first portion of the material layer and etching the exposed first portion of the material layer to form a first opening in the material layer by using the exposed first portions of the HM mandrel and the second spacer as a sub-etch-mask.

Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming a first flowable-material (FM) layer over a substrate. A top surface of the first FM layer in a first region is higher than a top surface of the first FM layer in a second region. The method also includes forming a sacrificial plug to cover the first FM layer in the first region, forming a second FM layer over the sacrificial plug in the first region and over the first FM layer in the second region, performing a first recessing process such that the second FM layer is removed in the first region and performing a second recessing process on the second FM layer in the second region while the first FM layer is protected by the sacrificial plug in the first region.

Abstract: Semiconductor structures are provided. The semiconductor structure includes a plurality of gate structures extending in a first direction formed over a substrate. The gate structures follow the following equation: 0.2 ? ? P gate ? ? min + 0.35 ? ? L gate ? ? min + 0.3 ? ? H gate ? ? min - 20 0.2 ? ? L gate ? ? min + 0.8 ? ? H gate ? ? min - 5 × 0.3 ? ? L gate ? ? min + 0.3 ? ? H gate ? ? min + 5 38 ? 0.32 Pgate min is the minimum value among gate pitches of the gate structures, and Lgate min is the minimum value among gate lengths of the gate structures. Hgate min is the minimum value among gate heights of the gate structures.

Abstract: A technique for patterning a workpiece such as an integrated circuit workpiece is provided. In an exemplary embodiment, the method includes receiving a dataset specifying a plurality features to be formed on the workpiece. A first patterning of a hard mask of the workpiece is performed based on a first set of features of the plurality of features, and a first spacer material is deposited on a sidewall of the patterned hard mask. A second patterning is performed based on a second set of features, and a second spacer material is deposited on a sidewall of the first spacer material. A third patterning is performed based on a third set of features. A portion of the workpiece is selectively processed using a pattern defined by a remainder of at least one of the patterned hard mask layer, the first spacer material, or the second spacer material.

Abstract: A semiconductor device includes a first gate structure, a second gate structure, a first source/drain structure and a second source/drain structure. The first gate structure includes a first gate electrode and a first cap insulating layer disposed on the first gate electrode. The second gate structure includes a second gate electrode and a first conductive contact layer disposed on the first gate electrode. The first source/drain structure includes a first source/drain conductive layer and a second cap insulating layer disposed over the first source/drain conductive layer. The second source/drain structure includes a second source/drain conductive layer and a second conductive contact layer disposed over the second source/drain conductive layer.

Abstract: A method for fabricating a semiconductor device includes forming a first material layer over a substrate, forming a middle layer over the first material layer, forming a first hard mask (HM) layer over the middle layer, forming a second HM layer over the first HM layer, forming a first trench in the second HM layer that extends into the first HM layer, forming a second trench in the second HM layer, The second trench is parallel to the first trench. The method also includes forming a first hole feature in the middle layer within the first trench by using the second HM layer and the first HM layer as a mask and forming a second hole feature in the middle layer within the second trench by using the second HM layer as a mask.

Abstract: The present disclosure relates to an integrated chip having a dual power rail structure. In some embodiments, the integrated chip has a first metal interconnect layer having a lower metal wire extending in a first direction. A second metal interconnect layer has a plurality of connection pins coupled to the lower metal wire by way of a first via layer and extending over the lower metal wire in a second direction perpendicular to the first direction. A third metal interconnect layer has an upper metal wire extending over the lower metal wire and the connection pins in the first direction. The upper metal wire is coupled to the connection pins by way of a second via layer arranged over the first via layer. Connecting the connection pins to the lower and upper metal wires reduces current density in connections to the connection pins, thereby reducing electromigration and/or IR issues.

Abstract: A technique for patterning a workpiece such as an integrated circuit workpiece is provided. In an exemplary embodiment, the method includes receiving a dataset specifying a plurality features to be formed on the workpiece. A first patterning of a hard mask of the workpiece is performed based on a first set of features of the plurality of features, and a first spacer material is deposited on a sidewall of the patterned hard mask. A second patterning is performed based on a second set of features, and a second spacer material is deposited on a sidewall of the first spacer material. A third patterning is performed based on a third set of features. A portion of the workpiece is selectively processed using a pattern defined by a remainder of at least one of the patterned hard mask layer, the first spacer material, or the second spacer material.

Abstract: A method for fabricating a semiconductor device includes forming a first hard mask (HM) layer over a material layer, forming a patterned second HM layer over the first HM layer. The patterned second HM layer has first trench extending along a first direction. The method also includes forming a patterned resist layer over the second HM layer. The patterned resist layer has a first line opening extending along a second direction, which is perpendicular to the first direction. The first line opening overlaps the first trench and exposes a portion of the second HM layer. The method also includes etching the first HM layer by using the patterned resist layer and the exposed portion of the second HM layer as an etch mask together to form a first hole feature in the first HM layer.