Abstract: Various embodiments of the invention provide techniques to ensure a layout for an integrated circuit is split-able. In a method embodiment, a layout is generated in a customer site having a layout library as inputs wherein the library provides exemplary layouts that have been verified to be spit-able and that can be used and layouts that can cause conflicts to avoid. A real-time odd cycle checker is also provided in which the checker identifies in real time conflict areas and odd cycles as they arise during layout generation. To reduce memory usage layouts of various devices may be separated so that each individual layout or a small number of layouts, rather than a large layout for the whole application circuit, can be checked against conflicts. Once the layout is ready at the customer site, it is sent to the foundry site to be decomposed into two masks and taped-out. Other embodiments are also disclosed.

Abstract: A method for fabricating an integrated circuit device is disclosed. The method includes providing a substrate; forming a semiconductor feature over the substrate; forming a first photoresist layer over the substrate; performing a lithography process on the first photoresist layer, such the first photoresist layer includes an opening therein that exposes the semiconductor feature; performing a stabilization process on the first photoresist layer; forming a second photoresist layer over the first photoresist layer, wherein the second photoresist layer fills the opening; and etching back the first and second photoresist layers until the semiconductor feature is exposed.

Abstract: A method of forming a photolithography mask including forming a first linear non-dense feature on the mask and forming a plurality of parallel linear assist features disposed substantially perpendicular to the at least one linear non-dense design feature. In an embodiment, the photolithography mask further includes a first transverse linear assist feature disposed substantially transverse to the plurality of parallel linear assist features.

Abstract: A method for fabricating an integrated circuit device is disclosed. The method includes providing a substrate; forming a semiconductor feature over the substrate; forming a first photoresist layer over the substrate; performing a lithography process on the first photoresist layer, such the first photoresist layer includes an opening therein that exposes the semiconductor feature; performing a stabilization process on the first photoresist layer; forming a second photoresist layer over the first photoresist layer, wherein the second photoresist layer fills the opening; and etching back the first and second photoresist layers until the semiconductor feature is exposed.

Abstract: A photolithography mask includes a design feature located in an isolated or semi-isolated region of the mask and a plurality of parallel linear assist features disposed substantially perpendicular to the design feature. The plurality of parallel linear assist features may include a first series of parallel assist features disposed on a first side of the design feature and perpendicularly thereto, and a second series of parallel assist features disposed on a second side of the design feature and perpendicularly thereto.

Abstract: Various embodiments of the invention provide techniques to ensure a layout for an integrated circuit is split-able. In a method embodiment, a layout is generated in a customer site having a layout library as inputs wherein the library provides exemplary layouts that have been verified to be spit-able and that can be used and layouts that can cause conflicts to avoid. A real-time odd cycle checker is also provided in which the checker identifies in real time conflict areas and odd cycles as they arise during layout generation. To reduce memory usage layouts of various devices may be separated so that each individual layout or a small number of layouts, rather than a large layout for the whole application circuit, can be checked against conflicts. Once the layout is ready at the customer site, it is sent to the foundry site to be decomposed into two masks and taped-out. Other embodiments are also disclosed.

Abstract: A method for photolithography in semiconductor manufacturing includes providing a mask with first and second focus planes for a wafer. The wafer includes corresponding first and second wafer regions. The first wafer region receives a first image during a first exposure utilizing the first focus plane. The second wafer region receives a second image during a second exposure utilizing the second focus plane.

Abstract: A photolithography mask includes a design feature located in an isolated or semi-isolated region of the mask and a plurality of parallel linear assist features disposed substantially perpendicular to the design feature. The plurality of parallel linear assist features may include a first series of parallel assist features disposed on a first side of the design feature and perpendicularly thereto, and a second series of parallel assist features disposed on a second side of the design feature and perpendicularly thereto.

Abstract: A semiconductor device and method of manufacture thereof wherein scattering bars are disposed on both sides of an isolated conductive line of a semiconductor device to improve the lithography results. The scattering bars have a sufficient width and are spaced a sufficient distance from the isolated conductive line so as to increase the depth of focus of the isolated conductive line during the patterning of the semiconductor device. The scattering bars are left remaining in the finished semiconductor device after the manufacturing process is completed.

Abstract: An isotropic-diffusion filling method uses a thermal process on a result structure comprising a photoresist layer and an organic material layer to create a cross-linking layer there between, which minimizes step height differences between isolated and dense via-pattern regions for optimizing a subsequent trench process and simplifying process steps.

Abstract: A photolithography mask includes a design feature located in an isolated or semi-isolated region of the mask and a plurality of parallel linear assist features disposed substantially perpendicular to the design feature.

Abstract: A method for photolithography in semiconductor manufacturing includes providing a mask with first and second focus planes for a wafer. The wafer includes corresponding first and second wafer regions. The first wafer region receives a first image during a first exposure utilizing the first focus plane. The second wafer region receives a second image during a second exposure utilizing the second focus plane.

Abstract: An isotropic-diffusion filling method uses a thermal process on a result structure comprising a photoresist layer and an organic material layer to create a cross-linking layer there between, which minimizes step height differences between isolated and dense via-pattern regions for optimizing a subsequent trench process and simplifying process steps.

Abstract: A semiconductor device and method of manufacture thereof wherein scattering bars are disposed on both sides of an isolated conductive line of a semiconductor device to improve the lithography results. The scattering bars have a sufficient width and are spaced a sufficient distance from the isolated conductive line so as to increase the depth of focus of the isolated conductive line during the patterning of the semiconductor device. The scattering bars are left remaining in the finished semiconductor device after the manufacturing process is completed.