Abstract: An electronic package is provided and includes an electronic module and a packaging module stacked on each other, where the electronic module includes a bridge component, a plurality of conductive pillars and an encapsulation layer encapsulating the bridge component and the plurality of conductive pillars, and the packaging module includes a circuit structure and a plurality of electronic elements disposed on the circuit structure, such that the packaging module is stacked on the electronic module via a plurality of supporting elements, and the plurality of electronic elements are electrically bridged with each other via the circuit structure, the plurality of supporting elements and the bridge component. Therefore, the electronic module and the packaging module are fabricated separately to prevent the bridge component from going through too many thermal processes, thereby preventing voids of the bridge component from transferring to the packaging module.

Abstract: An electronic package is provided in which an electronic structure is bonded onto a carrier structure via a plurality of conductive elements, where each of the conductive elements is connected to a single contact of the electronic structure via a plurality of conductive pillars. Therefore, when one of the conductive pillars fails, each of the conductive elements can still be electrically connected to the contact via the other of the conductive pillars to increase electrical conductivity.

Abstract: An electronic package and a method for fabricating the same are provided. The electronic package includes a stepped recess formed at a peripheral portion of a packaging module to release stress of the electronic package.

Abstract: An electronic package and a method for fabricating the same are provided. The electronic package includes a stepped recess formed at a peripheral portion of a packaging module to release stress of the electronic package.

Abstract: Semiconductor structures and methods of forming the same are provided. A semiconductor structure includes a substrate and an annular nanowire disposed over the substrate.

Abstract: Devices are described herein that include a first fin structure formed on a substrate. A second fin structure formed on the substrate. One or more gate structures are formed on the first fin structure and the second fin structure. A first in-fin source/drain region is associated with a first volume and is disposed between the first fin structure and the second fin structure. A fin-end source/drain region is associated with a second volume larger than the first volume, the first fin structure being disposed between the first in-fin source/drain region and the fin-end source/drain region. The gate structures, the first in-fin source/drain region, and the fin-end source/drain region are configured to form one or more transistors.

Abstract: A FinFET and methods for forming a FinFET are disclosed. A method includes forming trenches in a semiconductor substrate to form a fin, depositing an insulating material within the trenches, and removing a portion of the insulating material to expose sidewalls of the fin. The method also includes recessing a portion of the exposed sidewalls of the fin to form multiple recessed surfaces on the exposed sidewalls of the fin, wherein adjacent recessed surfaces of the multiple recessed surfaces are separated by a lattice shift. The method also includes depositing a gate dielectric on the recessed portion of the sidewalls of the fin and depositing a gate electrode on the gate dielectric.

Abstract: A shallow trench isolation (STI) structure is formed on a substrate. Part of the STI structure is removed to form a first fin structure and a second fin structure extending above a support structure on the substrate. A first part of the STI structure is located between the first fin structure and the second fin structure and has a first top surface higher than an interface between the first fin structure and the support structure. A second part of the STI structure is located adjacent to the first fin structure and has a second top surface lower than the interface between the first fin structure and the support structure. An etching process is performed to remove part of the first fin structure and the second fin structure. Part of the support structure adjacent to the second part of the STI structure is removed during the etching process.

Abstract: Devices are described herein that include a first fin structure formed on a substrate. A second fin structure formed on the substrate. One or more gate structures are formed on the first fin structure and the second fin structure. A first in-fin source/drain region is associated with a first volume and is disposed between the first fin structure and the second fin structure. A fin-end source/drain region is associated with a second volume larger than the first volume, the first fin structure being disposed between the first in-fin source/drain region and the fin-end source/drain region. The gate structures, the first in-fin source/drain region, and the fin-end source/drain region are configured to form one or more transistors.

Abstract: The present disclosure provides a quantum well fin field effect transistor (QWFinFET). The QWFinFET includes a semiconductor fin over a substrate and a combo quantum well (QW) structure over the semiconductor fin. The combo QW structure includes a QW structure over a top portion of the semiconductor fin and a middle portion of the semiconductor fin. The semiconductor fin and the QW comprise different semiconductor materials. The QWFinFET also includes a gate stack over the combo QW structure.

Abstract: An embodiment is a method including forming an epitaxial portion over a substrate, the epitaxial portion including a III-V material. A damaged material layer being on at least one surface of the epitaxial portion. The method further including oxidizing at least outer surfaces of the damaged material layer to form an oxide layer, selectively removing the oxide layer, and repeating the oxidizing and the selectively removing steps while at least a portion of the damaged material layer remains on the epitaxial portion.

Abstract: Semiconductor structures and methods of forming the same are provided. A semiconductor structure includes a substrate and an annular nanowire disposed over the substrate.

Abstract: According to another embodiment, a semiconductor structure is provided. The structure includes: a substrate; a first nanowire over the substrate; and a second nanowire over the substrate and substantially symmetric with the first nanowire.

Abstract: A FinFET and methods for forming a FinFET are disclosed. A method includes forming trenches in a semiconductor substrate to form a fin, depositing an insulating material within the trenches, and removing a portion of the insulating material to expose sidewalls of the fin. The method also includes recessing a portion of the exposed sidewalls of the fin to form multiple recessed surfaces on the exposed sidewalls of the fin, wherein adjacent recessed surfaces of the multiple recessed surfaces are separated by a lattice shift. The method also includes depositing a gate dielectric on the recessed portion of the sidewalls of the fin and depositing a gate electrode on the gate dielectric.

Abstract: The present disclosure provides a quantum well fin field effect transistor (QWFinFET). The QWFinFET includes a semiconductor fin over a substrate and a combo quantum well (QW) structure over the semiconductor fin. The combo QW structure includes a QW structure over a top portion of the semiconductor fin and a middle portion of the semiconductor fin. The semiconductor fin and the QW comprise different semiconductor materials. The QWFinFET also includes a gate stack over the combo QW structure.

Abstract: A finFET and methods for forming a finFET are disclosed. A structure comprises a substrate, a fin, a gate dielectric, and a gate electrode. The substrate comprises the fin. The fin has a major surface portion of a sidewall, and the major surface portion comprises at least one lattice shift. The at least one lattice shift comprises an inward or outward shift relative to a center of the fin. The gate dielectric is on the major surface portion of the sidewall. The gate electrode is on the gate dielectric.

Abstract: According to another embodiment, a semiconductor structure is provided. The structure includes: a substrate; a first nanowire over the substrate; and a second nanowire over the substrate and substantially symmetric with the first nanowire.

Abstract: The present disclosure provides a quantum well fin field effect transistor (QWFinFET). The QWFinFET includes a semiconductor fin over a substrate and a combo quantum well (QW) structure over the semiconductor fin. The combo QW structure includes a QW structure over a top portion of the semiconductor fin and a middle portion of the semiconductor fin. The semiconductor fin and the QW comprise different semiconductor materials. The QWFinFET also includes a gate stack over the combo QW structure.

Abstract: The present disclosure provides a quantum well fin field effect transistor (QWFinFET). The QWFinFET includes a semiconductor fin over a substrate and a combo quantum well (QW) structure over the semiconductor fin. The combo QW structure includes a QW structure over a top portion of the semiconductor fin and a middle portion of the semiconductor fin. The semiconductor fin and the QW comprise different semiconductor materials. The QWFinFET also includes a gate stack over the combo QW structure.

Abstract: A shallow trench isolation (STI) structure is formed on a substrate. Part of the STI structure is removed to form a first fin structure and a second fin structure extending above a support structure on the substrate. A first part of the STI structure is located between the first fin structure and the second fin structure and has a first top surface higher than an interface between the first fin structure and the support structure. A second part of the STI structure is located adjacent to the first fin structure and has a second top surface lower than the interface between the first fin structure and the support structure. An etching process is performed to remove part of the first fin structure and the second fin structure. Part of the support structure adjacent to the second part of the STI structure is removed during the etching process.