Patents by Inventor Yung-Wei Hsieh
Yung-Wei Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11955397Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a channel layer, a barrier layer, a compound semiconductor layer, a gate electrode, and a stack of dielectric layers. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The compound semiconductor layer is disposed on the barrier layer. The gate electrode is disposed on the compound semiconductor layer. The stack of dielectric layers is disposed on the gate electrode. The stack of dielectric layers includes layers having different etching rates.Type: GrantFiled: November 9, 2020Date of Patent: April 9, 2024Assignee: Vanguard International Semiconductor CorporationInventors: Shin-Cheng Lin, Cheng-Wei Chou, Ting-En Hsieh, Yi-Han Huang, Kwang-Ming Lin, Yung-Fong Lin, Cheng-Tao Chou, Chi-Fu Lee, Chia-Lin Chen, Shu-Wen Chang
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Patent number: 11955154Abstract: A sense amplifier circuit includes a sense amplifier, a switch and a temperature compensation circuit. The temperature compensation circuit provides a control signal having a positive temperature coefficient, based on which the switch provides reference impedance for temperature compensation. The sense amplifier includes a first input end coupled to a target bit and a second input end coupled to the switch. The sense amplifier outputs a sense amplifier signal based on the reference impedance and the impedance of the target bit.Type: GrantFiled: May 16, 2022Date of Patent: April 9, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Cheng-Tung Huang, Jen-Yu Wang, Po-Chun Yang, Yi-Ting Wu, Yung-Ching Hsieh, Jian-Jhong Chen, Chia-Wei Lee
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Patent number: 9508676Abstract: A semiconductor package structure having hollow chamber includes a bottom substrate having a bottom baseboard and a bottom metal layer formed on a disposing area of the bottom baseboard, a connection layer formed on the bottom metal layer, and a top substrate. The bottom metal layer has at least one corner having a first and a second outer lateral surface, and an outer connection surface. A first extension line is formed from a first extreme point of the first outer lateral surface, and a second extension line is formed from a second extreme point of the second outer lateral surface. A first exposing area of the bottom baseboard is formed by connecting the first and second extreme points and a cross point of the first and second extreme points. The top substrate connects to the connection layer to form a hollow chamber between the top and bottom substrates.Type: GrantFiled: September 9, 2015Date of Patent: November 29, 2016Assignee: CHIPBOND TECHNOLOGY CORPORATIONInventors: Cheng-Hung Shih, Yung-Wei Hsieh, Shu-Chen Lin, Fu-Yen Ho, Yen-Ting Chen
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Publication number: 20160318756Abstract: A process for manufacturing a semiconductor package having a hollow chamber includes providing a bottom substrate having a bottom plate, a ring wall and a slot, wherein the ring wall and the bottom plate form the slot; forming an under ball metallurgy layer on a surface of the ring wall; bumping a plurality of solder balls on a surface of the under ball metallurgy layer, each of the solder balls comprises a diameter, wherein a spacing is spaced apart between two adjacent solder balls; performing reflow soldering to the solder balls for making the solder balls melting and interconnecting to form a connection layer; connecting a top substrate to the bottom substrate, wherein the lot of the bottom substrate is sealed by the top substrate to form a hollow chamber used for accommodating an electronic device.Type: ApplicationFiled: June 11, 2015Publication date: November 3, 2016Inventors: Cheng-Hung Shih, Yung-Wei Hsieh, Shu-Chen Lin, Fu-Yen Ho, Yen-Ting Chen
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Publication number: 20160020166Abstract: A trace structure of fine-pitch pattern includes a connection portion, a first conductive wire portion and a second conductive wire portion, the first conductive wire portion comprises a first section and a second section connected to the first section, the first section connects to the connection portion, the second conductive wire portion comprises a third section and a fourth section connected to the third section, the third section connects to the connection portion, wherein an etching space closed on three sides is formed by the connection portion, the third section and the first section, a first spacing is defined between the third section and the first section, a second spacing is defined between the fourth section and the second section, wherein the first spacing is larger than the second spacing so as to make an metal layer within the etching space completely removed to avoid metal layer residues.Type: ApplicationFiled: October 16, 2014Publication date: January 21, 2016Inventors: Yung-Wei Hsieh, Cheng-Hung Shih, Kai-Yi Wang, Heh-Chang Huang, Po-Hao Chen
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Publication number: 20140367856Abstract: A semiconductor manufacturing process includes the following steps of providing a silicon substrate having at least one connection pad and a protection layer, forming a first seed layer having at least one first section and at least one second section, forming a first photoresist layer, forming a first buffer layer having a coupling portion and a cladding portion, removing the first photoresist layer, removing the second section of the first seed layer to form a first under bump metallurgy layer, forming a support layer on the protection layer and the first buffer layer, the first under bump metallurgy layer has a first ring wall, the first buffer layer has a second ring wall, wherein the first ring wall, the second ring wall and the cladding portion are cladded by the support layer, and forming a connection portion and covering the coupling portion with the connection portion.Type: ApplicationFiled: September 2, 2014Publication date: December 18, 2014Inventors: Cheng-Hung Shih, Yung-Wei Hsieh, Kai-Yi Wang
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Patent number: 8877629Abstract: A semiconductor manufacturing process includes the following steps of providing a silicon substrate having at least one connection pad and a protection layer, forming a first seed layer having at least one first section and at least one second section, forming a first photoresist layer, forming a first buffer layer having a coupling portion and a cladding portion, removing the first photoresist layer, removing the second section of the first seed layer to form a first under bump metallurgy layer, forming a support layer on the protection layer and the first buffer layer, the first under bump metallurgy layer has a first ring wall, the first buffer layer has a second ring wall, wherein the first ring wall, the second ring wall and the cladding portion are cladded by the support layer, and forming a connection portion and covering the coupling portion with the connection portion.Type: GrantFiled: January 17, 2013Date of Patent: November 4, 2014Assignee: Chipbond Technology CorporationInventors: Cheng-Hung Shih, Yung-Wei Hsieh, Kai-Yi Wang
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Publication number: 20140159234Abstract: A semiconductor manufacturing process includes the following steps of providing a silicon substrate having at least one connection pad and a protection layer, forming a first seed layer having at least one first section and at least one second section, forming a first photoresist layer, forming a first buffer layer having a coupling portion and a cladding portion, removing the first photoresist layer, removing the second section of the first seed layer to form a first under bump metallurgy layer, forming a support layer on the protection layer and the first buffer layer, the first under bump metallurgy layer has a first ring wall, the first buffer layer has a second ring wall, wherein the first ring wall, the second ring wall and the cladding portion are cladded by the support layer, and forming a connection portion and covering the coupling portion with the connection portion.Type: ApplicationFiled: January 17, 2013Publication date: June 12, 2014Applicant: CHIPBOND TECHNOLOGY CORPORATIONInventors: Cheng-Hung Shih, Yung-Wei Hsieh, Kai-Yi Wang
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Patent number: 8581239Abstract: A semiconductor structure comprises a carrier, a plurality of under bump metallurgy layers, a plurality of copper containing bumps and an organic barrier layer, wherein the carrier comprises a protective layer and a plurality of conductive pads, mentioned protective layer comprises a plurality of openings, the conductive pads exposed by the openings, mentioned under bump metallurgy layers being formed on the conductive pads, mentioned copper containing bumps being formed on the under bump metallurgy layers, each of the copper containing bumps comprises a top surface and a ring surface in connection with the top surface, mentioned organic barrier layer having a first coverage portion, and mentioned first coverage portion covers the top surface and the ring surface of each of the copper containing bumps.Type: GrantFiled: January 19, 2012Date of Patent: November 12, 2013Assignee: Chipbond Technology CorporationInventors: Cheng-Hung Shih, Shu-Chen Lin, Yung-Wei Hsieh, Jun-Yu Yeh
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Publication number: 20130256882Abstract: A method for manufacturing fine-pitch bumps comprises providing a silicon substrate; forming a titanium-containing metal layer having a plurality of first zones and a plurality of second zones on the silicon substrate; forming a photoresist layer on the titanium-containing metal layer; patterning the photoresist layer; forming a plurality of copper bumps having a plurality of first top surfaces and a plurality of first ring surfaces; heating the photoresist layer to form a plurality of body portions and removable portions; etching the photoresist layer; forming a plurality of bump protection layers on the titanium-containing metal layer, the first top surface and the first ring surface, each of the bump protection layers comprises a bump coverage portion; plating a plurality of gold layers at the bump coverage portion; eventually, removing the second zones to enable each of the first zones to form an under bump metallurgy layer.Type: ApplicationFiled: May 28, 2013Publication date: October 3, 2013Inventors: Cheng-Hung Shih, Yung-Wei Hsieh, Shu-Chen Lin, Cheng-Fan Lin, Hua-An Dai
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Publication number: 20130252374Abstract: A semiconductor packaging method includes providing a substrate having a plurality of pads, each of the pads comprises a first coupling surface having a plurality of first conductive contact areas and a plurality of first non-conductive contact areas; forming a conductible gel with anti-dissociation function on the substrate, said conductible gel includes a plurality of conductive particles and a plurality of anti-dissociation substances; mounting a chip on the substrate, said chip comprises a plurality of copper-containing bumps, each of the copper-containing bumps comprises a ring surface and a second coupling surface having a plurality of second conductive contact areas and a plurality of second non-conductive contact areas, wherein the conductive particles are electrically connected with the first conductive contact areas and the second conductive contact areas, said anti-dissociation substances are in contact with the second non-conductive contact area, and the ring surfaces are covered with the anti-disType: ApplicationFiled: May 14, 2013Publication date: September 26, 2013Applicant: CHIPBOND TECHNOLOGY CORPORATIONInventors: Cheng-Hung Shih, Shu-Chen Lin, Cheng-Fan Lin, Yung-Wei Hsieh, Bo-Shiun Jiang
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Publication number: 20130249089Abstract: A method for manufacturing fine-pitch bumps comprises the steps of providing a silicon substrate; forming a titanium-containing metal layer on the silicon substrate, wherein the titanium-containing metal layer comprises a plurality of first zones and a plurality of second zones; forming a photoresist layer on the titanium-containing metal layer; patterning the photoresist layer to form a plurality of opening slots; forming a plurality of copper bumps at the opening slots, wherein each of the copper bumps comprises a first top surface and a ring surface; heating the photoresist layer to form a plurality of body portions and a plurality of removable portions; etching the photoresist layer; and removing the second zones to enable each of the first zones to form an under bump metallurgy layer having a bearing portion and an extending portion.Type: ApplicationFiled: May 14, 2013Publication date: September 26, 2013Applicant: CHIPBOND TECHNOLOGY CORPORATIONInventors: Cheng-Hung Shih, Yung-Wei Hsieh, Shu-Chen Lin, Cheng-Fan Lin, Hua-An Dai
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Publication number: 20130249081Abstract: A method for manufacturing fine-pitch bumps comprises providing a silicon substrate; forming a titanium-containing metal layer having a plurality of first zones and a plurality of second zones on the silicon substrate; forming a photoresist layer on the titanium-containing metal layer; patterning the photoresist layer; forming a plurality of copper bumps having a plurality of first top surfaces and a plurality of first ring surfaces; heating the photoresist layer to form a plurality of body portions and removable portions; etching the photoresist layer; forming a plurality of bump protection layers on the titanium-containing metal layer, the first top surface and the first ring surface, each of the bump protection layers comprises a bump coverage portion; plating a plurality of gold layers at the bump coverage portion; eventually, removing the second zones to enable each of the first zones to form an under bump metallurgy layer.Type: ApplicationFiled: March 22, 2012Publication date: September 26, 2013Applicant: CHIPBOND TECHNOLOGY CORPORATIONInventors: Cheng-Hung Shih, Yung-Wei Hsieh, Shu-Chen Lin, Cheng-Fan Lin, Hua-An Dai
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Patent number: 8530344Abstract: A method for manufacturing fine-pitch bumps comprises providing a silicon substrate; forming a titanium-containing metal layer having a plurality of first zones and a plurality of second zones on the silicon substrate; forming a photoresist layer on the titanium-containing metal layer; patterning the photoresist layer; forming a plurality of copper bumps having a plurality of first top surfaces and a plurality of first ring surfaces; heating the photoresist layer to form a plurality of body portions and removable portions; etching the photoresist layer; forming a plurality of bump protection layers on the titanium-containing metal layer, the first top surface and the first ring surface, each of the bump protection layers comprises a bump coverage portion; plating a plurality of gold layers at the bump coverage portion; eventually, removing the second zones to enable each of the first zones to form an under bump metallurgy layer.Type: GrantFiled: March 22, 2012Date of Patent: September 10, 2013Assignee: Chipbond Technology CorporationInventors: Cheng-Hung Shih, Yung-Wei Hsieh, Shu-Chen Lin, Cheng-Fan Lin, Hua-An Dai
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Publication number: 20130214407Abstract: A semiconductor packaging method includes providing a substrate having a plurality of pads, each of the pads comprises a first coupling surface having a plurality of first conductive contact areas and a plurality of first non-conductive contact areas; forming a conductible gel with anti-dissociation function on the substrate, said conductible gel includes a plurality of conductive particles and a plurality of anti-dissociation substances; mounting a chip on the substrate, said chip comprises a plurality of copper-containing bumps, each of the copper-containing bumps comprises a ring surface and a second coupling surface having a plurality of second conductive contact areas and a plurality of second non-conductive contact areas, wherein the conductive particles are electrically connected with the first conductive contact areas and the second conductive contact areas, said anti-dissociation substances are in contact with the second non-conductive contact area, and the ring surfaces are covered with the anti-disType: ApplicationFiled: February 16, 2012Publication date: August 22, 2013Applicant: CHIPBOND TECHNOLOGY CORPORATIONInventors: Cheng-Hung Shih, Shu-Chen Lin, Cheng-Fan Lin, Yung-Wei Hsieh, Bo-Shiun Jiang
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Publication number: 20130214419Abstract: A semiconductor packaging method includes providing a substrate having a plurality of connection pads; mounting a chip on the substrate, wherein the chip comprises a plurality of copper-containing bumps directly coupled to the connection pads, and each of the copper-containing bumps comprises a ring surface; forming an anti-dissociation gel between the substrate and the chip, wherein the anti-dissociation gel comprises a plurality of anti-dissociation substances, and the ring surfaces of the copper-containing bumps are covered by the anti-dissociation substances.Type: ApplicationFiled: February 16, 2012Publication date: August 22, 2013Applicant: CHIPBOND TECHNOLOGY CORPORATIONInventors: Cheng-Hung Shih, Shu-Chen Lin, Cheng-Fan Lin, Yung-Wei Hsieh, Ming-Yi Liu
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Patent number: 8501614Abstract: A method for manufacturing fine-pitch bumps comprises the steps of providing a silicon substrate; forming a titanium-containing metal layer on the silicon substrate, wherein the titanium-containing metal layer comprises a plurality of first zones and a plurality of second zones; forming a photoresist layer on the titanium-containing metal layer; patterning the photoresist layer to form a plurality of opening slots; forming a plurality of copper bumps at the opening slots, wherein each of the copper bumps comprises a first top surface and a ring surface; heating the photoresist layer to form a plurality of body portions and a plurality of removable portions; etching the photoresist layer; and removing the second zones to enable each of the first zones to form an under bump metallurgy layer having a bearing portion and an extending portion.Type: GrantFiled: March 22, 2012Date of Patent: August 6, 2013Assignee: Chipbond Technology CorporationInventors: Cheng-Hung Shih, Yung-Wei Hsieh, Shu-Chen Lin, Cheng-Fan Lin, Hua-An Dai
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Patent number: 8497579Abstract: A semiconductor packaging method includes providing a substrate having a plurality of pads, each of the pads comprises a first coupling surface having a plurality of first conductive contact areas and a plurality of first non-conductive contact areas; forming a conductible gel with anti-dissociation function on the substrate, said conductible gel includes a plurality of conductive particles and a plurality of anti-dissociation substances; mounting a chip on the substrate, said chip comprises a plurality of copper-containing bumps, each of the copper-containing bumps comprises a ring surface and a second coupling surface having a plurality of second conductive contact areas and a plurality of second non-conductive contact areas, wherein the conductive particles are electrically connected with the first conductive contact areas and the second conductive contact areas, said anti-dissociation substances are in contact with the second non-conductive contact area, and the ring surfaces are covered with the anti-disType: GrantFiled: February 16, 2012Date of Patent: July 30, 2013Assignee: Chipbond Technology CorporationInventors: Cheng-Hung Shih, Shu-Chen Lin, Cheng-Fan Lin, Yung-Wei Hsieh, Bo-Shiun Jiang
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Publication number: 20130187265Abstract: A semiconductor structure comprises a carrier, a plurality of under bump metallurgy layers, a plurality of copper containing bumps and an organic barrier layer, wherein the carrier comprises a protective layer and a plurality of conductive pads, mentioned protective layer comprises a plurality of openings, the conductive pads exposed by the openings, mentioned under bump metallurgy layers being formed on the conductive pads, mentioned copper containing bumps being formed on the under bump metallurgy layers, each of the copper containing bumps comprises a top surface and a ring surface in connection with the top surface, mentioned organic barrier layer having a first coverage portion, and mentioned first coverage portion covers the top surface and the ring surface of each of the copper containing bumps.Type: ApplicationFiled: January 19, 2012Publication date: July 25, 2013Applicant: CHIPBOND TECHNOLOGY CORPORATIONInventors: Cheng-Hung Shih, Shu-Chen Lin, Yung-Wei Hsieh, Jun-Yu Yeh
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Publication number: 20130183823Abstract: A bumping process includes providing a silicon substrate, forming a titanium-containing metal layer on the silicon substrate, wherein the titanium-containing metal layer comprises a plurality of first areas and a plurality of second areas, forming a photoresist layer on the titanium-containing metal layer, patterning the photoresist layer to form a plurality of opening slots corresponded to the first areas of the titanium-containing metal layer, forming a plurality of copper bumps at the opening slots, proceeding a heat procedure, forming a plurality of bump isolation layers on the copper bumps, forming a plurality of connective layers on the bump isolation layers, removing the photoresist layer, removing the second areas and enabling each the first areas to form an under bump metallurgy layer.Type: ApplicationFiled: January 18, 2012Publication date: July 18, 2013Applicant: CHIPBOND TECHNOLOGY CORPORATIONInventors: Chih-Ming Kuo, Hua-An Dai, Cheng-Fan Lin, Yie-Chuan Chiu, Yung-Wei Hsieh