Abstract: A motor stator includes a body member having multiple wire-winding grooves that is formed of a stack of silicon steel plates and defines axially a middle section and two end sections, the wire-dinging grooves in the end sections being greater than in the middle section, two wire racks each having foot tubes respectively inserted into the end sections of the body member in the wire-winding grooves beyond the middle section, the foot tubes having an inner diameter not less than the part of the wire-winding grooves corresponding to the middle section, and insulation sheets having a length greater than the height of the middle section of the body member and being respectively set in the wire-winding grooves and the corresponding foot tubes.

Abstract: The present invention discloses a line-width inspection device. The line-width inspection device has a platform, an image capturing device, a main light source device and at least one compensation light source device. The image capturing device is mounted above the platform, aligned with an inspection area of the platform and captures images of a pattern under inspection in the inspection area. The main light source device is disposed above the platform and correspondingly provides forward illumination to the inspection area, and an incident direction thereof is perpendicular to the platform. The at least one compensation light source device is mounted above the platform and provides compensation illumination to the inspection area. The additional compensation light source device can prevent edges of the pattern under inspection from occurring shadows and affecting image capturing, so as to enhance precision of image capturing.

Abstract: A method for handling multiple network packets is provided. The method is suitable for an embedded system connected to a network, wherein the embedded system includes a network device driver module and a simplified TCP/IP stack module. First, a plurality of network packets are received by the network device driver module. Then, each time when the network device driver module copies one of the network packets into a buffer of the simplified TCP/IP stack module, a packet length of the copied network packet is recorded in a packet information table. Thereafter, the network packets are obtained from the buffer one at a time according to the packet lengths recorded in the packet information table and analyzed by the simplified TCP/IP stack module. Thereby, multiple network packets can be handled correctly even in an environment wherein a simplified TCP/IP stack is used.

Abstract: An amplitude modulation circuit in a polar transmitter includes a digital-to-analog converter (DAC), a filter, a gm stage, and a calibration module. The DAC is arranged to be coupled to an amplitude modulation signal input in a normal mode. The filter is coupled to the DAC, and the gm stage is coupled to the filter. The calibration module has an input coupled to the gm stage, and an output coupled to a node on a path between the DAC and the gm stage. A method for calibrating an amplitude offset in the polar transmitter includes: generating an amplitude offset calibration signal according to an amplitude modulation signal generated from the gm stage; and transmitting the amplitude offset calibration signal via the output of the calibration module to a node on a path between the DAC and the gm stage so as to calibrate the amplitude offset.

Abstract: An amplitude modulation circuit in a polar transmitter and a method for calibrating amplitude offset in the polar transmitter are provided. The amplitude modulation circuit includes a digital-to-analog converter (DAC), a low pass filter (LPF), a gm stage, and a calibration module. The DAC is coupled to an amplitude modulation signal input. The LPF is coupled to the DAC, and the gm stage is coupled to the LPF. The calibration module has an input coupled to the gm stage, and an output coupled to a node on a path between the DAC and the gm stage. The method includes: generating an amplitude offset calibration signal according to an amplitude modulation signal generated from the gm stage; and transmitting the amplitude offset calibration signal via the output of the calibration module to a node on a path between the DAC and the gm stage so as to calibrate the amplitude offset.

Abstract: An operating circuit includes a differential amplifier stage, which has a first input node for receiving a first input signal of a differential input, a second input node for receiving a second input signal of the differential input, a first output node for outputting a first output signal of a differential output, and a second output node for outputting a second output signal of the differential output; an offset current stage coupled to the first output node and the second output node for inducing a first offset current at the first output node and a second offset current at the second output node; and a first clamping device coupled to the first output node for selectively clamping an output voltage at the first output node according to the first output signal at the first output node.

Abstract: A method and a system for downloading network data into a multimedia player are provided. In the present method, a data getting instruction sent by the multimedia player is received and accordingly a webpage source code is captured. Then, a web server corresponding to the webpage source code is identified, and the webpage source code is parsed according to a type information of the web server to obtain a plurality of data url links conforming to a data attribute. Finally, network data corresponding to each of the data url links is downloaded through a network and provided to the multimedia player.

Abstract: An amplitude modulation circuit in a polar transmitter and a method for calibrating amplitude offset in the polar transmitter are provided. The amplitude modulation circuit includes a digital-to-analog converter (DAC), a low pass filter (LPF), a gm stage, and a calibration module. The DAC is coupled to an amplitude modulation signal input. The LPF is coupled to the DAC, and the gm stage is coupled to the LPF. The calibration module has an input coupled to the gm stage, and an output coupled to a node on a path between the DAC and the gm stage. The method includes: generating an amplitude offset calibration signal according to an amplitude modulation signal generated from the gm stage; and transmitting the amplitude offset calibration signal via the output of the calibration module to a node on a path between the DAC and the gm stage so as to calibrate the amplitude offset.

Abstract: In a continuous-time sigma-delta modulator, by using dynamic element matching (DEM) with respect to comparators of a quantizer, or by generating a plurality of candidate DEM results in advance for selecting an approximate DEM result, a time slot for DEM operations in each cycle of a sampling signal is significantly increased without being rushed.

Abstract: In a continuous-time sigma-delta modulator, by using dynamic element matching (DEM) with respect to comparators of a quantizer, or by generating a plurality of candidate DEM results in advance for selecting an approximate DEM result, a time slot for DEM operations in each cycle of a sampling signal is significantly increased without being rushed.

Abstract: A method for handling multiple network packets is provided. The method is suitable for an embedded system connected to a network, wherein the embedded system includes a network device driver module and a simplified TCP/IP stack module. First, a plurality of network packets are received by the network device driver module. Then, each time when the network device driver module copies one of the network packets into a buffer of the simplified TCP/IP stack module, a packet length of the copied network packet is recorded in a packet information table. Thereafter, the network packets are obtained from the buffer one at a time according to the packet lengths recorded in the packet information table and analyzed by the simplified TCP/IP stack module. Thereby, multiple network packets can be handled correctly even in an environment wherein a simplified TCP/IP stack is used.

Abstract: A signal processing system and related method are disclosed. The signal processing system includes a signal processing module, powered by a low supply voltage, for processing signals; and an interface module, coupled to the signal processing module, powered by a high supply voltage, for outputting signals generated from the signal processing module; wherein the interface module comprises a plurality of high-voltage functional blocks integrated therein, and each of the functional blocks is configured to perform a predetermined interface functionality. In this way, the bill-of-material (BOM) cost can be reduced.

Abstract: An operating circuit includes a differential amplifier stage, which has a first input node for receiving a first input signal of a differential input, a second input node for receiving a second input signal of the differential input, a first output node for outputting a first output signal of a differential output, and a second output node for outputting a second output signal of the differential output; an offset current stage coupled to the first output node and the second output node for inducing a first offset current at the first output node and a second offset current at the second output node; and a first clamping device coupled to the first output node for selectively clamping an output voltage at the first output node according to the first output signal at the first output node.

Abstract: An offset calibration system of a control loop at least comprises an optical-to-electrical converter and an electrical-to-optical converter. The optical-to-electrical converter generates a pre-output signal and then transmits the pre-output signal to the electrical-to-optical converter to amplify. The offset calibration system comprises a comparator, an offset calibration module, and a determination circuit. The comparator compares the pre-output signal with a predetermined pre-reference signal to generate a pre-compared signal. The offset calibration module stores a predetermined and adjustable offset calibration value for adding to the pre-output signal.

Abstract: The stator structures including: a stator base has a plurality of stator slots and every stator slot is including two outside tunnels and an internal tunnel. The width of every outside tunnels is wider than the internal tunnel. Tow stator arrangements are provided on end of the stator base respectively. Every stator arrangement has a plurality of fixing portions and the fixing portions correspond to the outside tunnels. The thickness of every fixing portion is smaller or equal to the distance between the wall of every outside tunnel and the wall of every internal tunnel. Hence, every insulation plate occupies less space of said stator slot and the volume of every coil can be increased.

Abstract: A peak detection circuit with double peak detection stages includes an analog peak detector, an analog-to-digital converter (ADC), and a digital peak detector. The analog peak detector receives an analog input signal, detects a peak value of the analog input signal with a first period, and outputs an analog peak signal. The ADC receives the analog peak signal and converts it into a digital signal. The digital peak detector receives the digital signal, detects the peak value of the digital signal with a second period longer than the first period, and outputs a digital peak signal. Therefore, the analog peak signal will not decay seriously due to the leakage and the digital peak signal can hold the digital peak value for a long time.

Abstract: The present invention is an optical detection system to detect various areas of an optical storage medium. The optical detection system comprises a pickup head, a signal adder and an adding comparator. The pickup head have a light source for providing an incident light beam to the data area and the header, and generating the corresponding reflective light beam. The pickup head detects the reflective light beam to generate left-side detection signals and right-side detection signals. The signal adder adds the amplitudes of the left-side detection signal and the right-side detection signal to generate an adding signal. The adding comparator compares the adding signal with a predetermined adding reference signal to generate a compared adding signal. According to the compared adding signal, the optical detection system can determine that the reflective light beam detected by the pickup head comes from the data area or the header.

Abstract: An offset calibration system of a control loop at least comprises an optical-to-electrical converter and an electrical-to-optical converter. The optical-to-electrical converter generates a pre-output signal and then transmits the pre-output signal to the electrical-to-optical converter to amplify. The offset calibration system comprises a comparator, an offset calibration module, and a determination circuit. The comparator compares the pre-output signal with a predetermined pre-reference signal to generate a pre-compared signal. The offset calibration module stores a predetermined and adjustable offset calibration value for adding to the pre-output signal.

Abstract: An offset calibration system of a control loop at least comprises a pre-amplifier circuit and a post-amplifier circuit. The pre-amplifier circuit generates a pre-output signal and then transmits the pre-output signal to the post-amplifier circuit to amplify. The offset calibration system comprises a comparator, an offset calibration module, and a determination circuit. The comparator compares the pre-output signal with a predetermined pre-reference signal to generate a pre-compared signal. The offset calibration module stores a predetermined and adjustable offset calibration value for adding to the pre-output signal. The determination circuit adjusts the offset calibration value based on the pre-compared signal, so the offset calibration value can be added to the pre-output signal dynamically to compensate and calibrate the offset of the pre-output signal caused by the pre-amplifier circuit to avoid the post-amplifier circuit amplifying the offset of the pre-output signal again.

Abstract: A peak detection circuit with double peak detection stages includes an analog peak detector, an analog-to-digital converter (ADC), and a digital peak detector. The analog peak detector receives an analog input signal, detects a peak value of the analog input signal with a first cycle, and outputs an analog peak signal. The ADC receives the analog peak signal and converts it into a digital signal. The digital peak detector receives the digital signal, detects the peak value of the digital signal with a second cycle, and outputs a digital peak signal. The time of the first cycle is shorter than the time of the second cycle. Therefore, the analog peak signal will not decay seriously due to the leakage and the digital peak signal can hold the digital peak value for a long time.