Abstract: A semiconductor device includes stack structures each including a first conductive layer, a substrate disposed under the stack structures, first impurity regions disposed in the substrate, and at least one trench passing through the stack structures and disposed above the first impurity regions.

Abstract: A semiconductor device includes stack structures each including a first conductive layer, a substrate disposed under the stack structures, first impurity regions disposed in the substrate, and at least one trench passing through the stack structures and disposed above the first impurity regions.

Abstract: A semiconductor device includes stack structures each including a first conductive layer, a substrate disposed under the stack structures, first impurity regions disposed in the substrate, and at least one trench passing through the stack structures and disposed above the first impurity regions.

Abstract: A chemical mechanical polishing (CMP) method includes preparing a polishing pad, determining a first load to be applied to a conditioning disk during conditioning of the polishing pad and a first indentation depth at which tips of the conditioning disk are inserted into the polishing pad when the first load is applied to the conditioning disk, preparing a conditioning disk, and positioning the conditioning disk on the polishing pad and conditioning a surface of the polishing pad by using the conditioning disk while applying the first load to the conditioning disk.

Abstract: Provided herein is a semiconductor memory device. The semiconductor memory device may include channel layers protruding away from a substrate. The semiconductor memory device may include a plurality of pads respectively coupled to the channel layers. The widths of the pads may or may not be increased depending on a bending of the channel layers.

Abstract: A semiconductor memory device includes a cell array region formed on a substrate, a word line contact region, and a page buffer region coupled to the cell array region through bit lines, wherein at least one of the bit lines has a curved structure toward the word line contact region. According to an embodiment, a misalignment between a cell plug and a contact plug caused by a natural cell plug bending phenomenon may be reduced to improve operational reliability of a semiconductor memory device.

Abstract: A semiconductor device includes stack structures each including a first conductive layer, a substrate disposed under the stack structures, first impurity regions disposed in the substrate, and at least one trench passing through the stack structures and disposed above the first impurity regions.

Abstract: A chemical mechanical polishing method includes providing a pad conditioner, such that the pad conditioner includes a base and a plurality of tips protruding from a surface of the base, adjusting a surface roughness of an upper surface of each tip of the plurality of tips, and adjusting a polishing rate of chemical mechanical polishing using the adjusted surface roughness of the upper surfaces of the plurality of tips.

Abstract: A semiconductor memory device includes a cell array region formed on a substrate, a word line contact region, and a page buffer region coupled to the cell array region through bit lines, wherein at least one of the bit lines has a curved structure toward the word line contact region. According to an embodiment, a misalignment between a cell plug and a contact plug caused by a natural cell plug bending phenomenon may be reduced to improve operational reliability of a semiconductor memory device.

Abstract: A semiconductor memory device includes a cell array region formed on a substrate, a word line contact region, and a page buffer region coupled to the cell array region through bit lines, wherein at least one of the bit lines has a curved structure toward the word line contact region. According to an embodiment, a misalignment between a cell plug and a contact plug caused by a natural cell plug bending phenomenon may be reduced to improve operational reliability of a semiconductor memory device.

Abstract: A semiconductor memory device includes a cell array region formed on a substrate, a word line contact region, and a page buffer region coupled to the cell array region through bit lines, wherein at least one of the bit lines has a curved structure toward the word line contact region. According to an embodiment, a misalignment between a cell plug and a contact plug caused by a natural cell plug bending phenomenon may be reduced to improve operational reliability of a semiconductor memory device.

Abstract: Provided herein is a semiconductor memory device. The semiconductor memory device may include channel layers protruding away from a substrate. The semiconductor memory device may include a plurality of pads respectively coupled to the channel layers. The widths of the pads may or may not be increased depending on a bending of the channel layers.

Abstract: A chemical mechanical polishing (CMP) method includes preparing a polishing pad, determining a first load to be applied to a conditioning disk during conditioning of the polishing pad and a first indentation depth at which tips of the conditioning disk are inserted into the polishing pad when the first load is applied to the conditioning disk, preparing a conditioning disk, and positioning the conditioning disk on the polishing pad and conditioning a surface of the polishing pad by using the conditioning disk while applying the first load to the conditioning disk.

Abstract: The present invention relates to a proximity luminance sensor obtained by assembling a housing array to a printed circuit board array using an adhesive layer, prior to separation into individual proximity luminance sensors, thereby preventing contamination or damage to lenses, decreasing the optical interference phenomenon, reducing the manufacturing cost and manufacturing time, and thus substantially improving productivity.

Abstract: A dual damascene structure and a method of forming a dual damascene structure are disclosed. The dual damascene structure includes an insulation member, a single crystal member and a filling member. The insulation member has an opening having a dual damascene shape. The filling member is formed on a side face of the opening. The single crystal member contacts the filling member. The single crystal member fills up the opening. In order to form a dual damascene structure, an insulating member having an opening partially filled with a preliminary single crystal member is formed. The filling member is formed on a side face of the opening. The preliminary single crystal member epitaxially grows to fill up the opening. Because the filling member is positioned between the single crystal member and the insulation member, void formation may be reduced between the single crystal member and the insulation member.

Abstract: A dual damascene structure and a method of forming a dual damascene structure are disclosed. The dual damascene structure includes an insulation member, a single crystal member and a filling member. The insulation member has an opening having a dual damascene shape. The filling member is formed on a side face of the opening. The single crystal member contacts the filling member. The single crystal member fills up the opening. In order to form a dual damascene structure, an insulating member having an opening partially filled with a preliminary single crystal member is formed. The filling member is formed on a side face of the opening. The preliminary single crystal member epitaxially grows to fill up the opening. Because the filling member is positioned between the single crystal member and the insulation member, void formation may be reduced between the single crystal member and the insulation member.

Abstract: A dual damascene structure and a method of forming a dual damascene structure are disclosed. The dual damascene structure includes an insulation member, a single crystal member and a filling member. The insulation member has an opening having a dual damascene shape. The filling member is formed on a side face of the opening. The single crystal member contacts the filling member. The single crystal member fills up the opening. In order to form a dual damascene structure, an insulating member having an opening partially filled with a preliminary single crystal member is formed. The filling member is formed on a side face of the opening. The preliminary single crystal member epitaxially grows to fill up the opening. Because the filling member is positioned between the single crystal member and the insulation member, void formation may be reduced between the single crystal member and the insulation member.

Abstract: A dual damascene structure and a method of forming a dual damascene structure are disclosed. The dual damascene structure includes an insulation member, a single crystal member and a filling member. The insulation member has an opening having a dual damascene shape. The filling member is formed on a side face of the opening. The single crystal member contacts the filling member. The single crystal member fills up the opening. In order to form a dual damascene structure, an insulating member having an opening partially filled with a preliminary single crystal member is formed. The filling member is formed on a side face of the opening. The preliminary single crystal member epitaxially grows to fill up the opening. Because the filling member is positioned between the single crystal member and the insulation member, void formation may be reduced between the single crystal member and the insulation member.

Abstract: In a method of manufacturing a semiconductor device, a preliminary insulating layer is formed on a substrate. A photoresist pattern is formed on the preliminary insulating layer. A central portion of the preliminary insulating layer is partially etched using the photoresist pattern as an etch mask to form a preliminary insulating layer pattern including a central portion and a peripheral portion on the substrate. The peripheral portion of the photoresist pattern is higher than that of the central portion of the preliminary insulating layer pattern. The preliminary insulating layer pattern is polished to form a planarized insulating layer on the substrate.

Abstract: According to embodiments of the invention, a height of a capacitor lower electrode is increased. Portions of the lower electrode and an interlayer insulating layer are etched within the interlayer insulating layer that is formed with the lower electrode thereon, so that a trench having a double damascene structure is formed. A dielectric layer and an upper electrode are formed within the trench. Therefore, shorts between metal interconnects caused by misalignments during formation of the upper electrode are prevented and consistent capacitance values may be secured.