Patents by Inventor Yunhui Chu

Yunhui Chu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240088069
    Abstract: Disclosed herein are integrated circuit (IC) supports with microstrips, and related embodiments. For example, an IC support may include a plurality of microstrips and a plurality of conductive segments. Individual ones of the conductive segments may be at least partially over at least two microstrips, a dielectric material may be between the plurality of microstrips and the plurality of conductive segments, and the conductive segments are included in a tape.
    Type: Application
    Filed: February 26, 2021
    Publication date: March 14, 2024
    Applicant: Intel Corporation
    Inventors: Wenzhi Wang, Xiaoning Ye, Yunhui Chu, Chunfei Ye, James A. McCall
  • Publication number: 20230214669
    Abstract: Decision feedback equalization (DFE) training time in a memory device is reduced through the use of a hybrid search to select values of tap coefficients for taps in the DFE. The hybrid search includes two searches. A first search is performed to identify initial values of tap coefficients, a second search uses the initial values of tap coefficients to find the final values of tap coefficients.
    Type: Application
    Filed: March 13, 2023
    Publication date: July 6, 2023
    Inventors: Wenzhi WANG, Yunhui CHU, James A. McCALL, Chunfei YE, Tonia M. ROSE, Caroline GRIMES
  • Publication number: 20210399764
    Abstract: An apparatus comprises a crosstalk cancelation circuit comprising a plurality of taps to output signals based on a signal transmitted via a first data line; and a summation circuit to combine a signal received by a second data line with the signals output by the plurality of taps to reduce near-end crosstalk present in the signal received by the second data line.
    Type: Application
    Filed: September 1, 2021
    Publication date: December 23, 2021
    Applicant: Intel Corporation
    Inventors: Jingbo Li, Beom-Taek Lee, Jong-Ru Guo, Yunhui Chu, Chunfei Ye, Kai Xiao
  • Patent number: 11116072
    Abstract: An apparatus is described. The apparatus includes a semiconductor chip having cross-talk noise cancellation circuitry disposed between a disturber trace and a trace to be protected from cross-talk noise emanating from the disturber trace. The trace is to be coupled to a receiver disposed on a different semiconductor chip.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: September 7, 2021
    Assignee: Intel Corporation
    Inventors: Jun Liao, Zhen Zhou, James A. McCall, Jong-Ru Guo, Xiang Li, Yunhui Chu, Zuoguo Wu
  • Patent number: 10965047
    Abstract: Embodiments may relate to a connector. The connector may include a plurality of connector pins that are to communicatively couple an element of a printed circuit board (PCB) with an element of an electronic device when the element of the PCB and the element of the electronic device are coupled with the connector. The connector may also include an active circuit that is communicatively coupled with a pin of the plurality of pins. The active circuit may be configured to match an impedance of the element of the PCB with an impedance of the element of the electronic device. Other embodiments may be described or claimed.
    Type: Grant
    Filed: June 4, 2019
    Date of Patent: March 30, 2021
    Assignee: Intel Corporation
    Inventors: Jong-Ru Guo, Yunhui Chu, Jun Liao, Kai Xiao, Jingbo Li, Yuanhong Zhao, Mo Liu, Beomtaek Lee, James A. McCall, Jaejin Lee, Xiaoning Ye, Zuoguo Wu, Xiang Li
  • Publication number: 20200313722
    Abstract: An apparatus comprises a first data line coupled to a first driver; a second data line coupled to a second driver; and a crosstalk cancelation circuit comprising a third driver coupled between the first data line and the second data line, the crosstalk cancelation circuit to compensate for far end crosstalk introduced from the first data line to the second data line.
    Type: Application
    Filed: June 16, 2020
    Publication date: October 1, 2020
    Applicant: Intel Corporation
    Inventors: James Alexander McCall, Yunhui Chu, Christopher Philip Mozak, Derek M. Conrow, Christian Karl
  • Patent number: 10729002
    Abstract: Techniques and mechanisms for mitigating signal deterioration in communications between two circuit boards. In an embodiment, a packaged device accommodates coupling to a first circuit board which, in turn, accommodates connection to a second circuit board. In one such embodiment, an amplifier circuit of the packaged device includes an amplifier circuit which comprises a variable resistor and an active circuit element coupled thereto. The device receives via one of the circuit boards a control signal and a voltage which configure the amplifier circuit to provide an impedance matching for communication between the circuit boards. In another embodiment, the device comprises multiple common gate amplifiers which are variously configurable each to provide a respective impedance matching for communications between a motherboard and a dual in-line memory module.
    Type: Grant
    Filed: July 18, 2019
    Date of Patent: July 28, 2020
    Assignee: Intel Corporation
    Inventors: Jun Liao, Xiang Li, Yunhui Chu, Jong-Ru Guo, James McCall
  • Publication number: 20190342990
    Abstract: Techniques and mechanisms for mitigating signal deterioration in communications between two circuit boards. In an embodiment, a packaged device accommodates coupling to a first circuit board which, in turn, accommodates connection to a second circuit board. In one such embodiment, an amplifier circuit of the packaged device includes an amplifier circuit which comprises a variable resistor and an active circuit element coupled thereto. The device receives via one of the circuit boards a control signal and a voltage which configure the amplifier circuit to provide an impedance matching for communication between the circuit boards. In another embodiment, the device comprises multiple common gate amplifiers which are variously configurable each to provide a respective impedance matching for communications between a motherboard and a dual in-line memory module.
    Type: Application
    Filed: July 18, 2019
    Publication date: November 7, 2019
    Inventors: Jun Liao, Xiang Li, Yunhui Chu, Jong-Ru Guo, James McCall
  • Patent number: 10467160
    Abstract: A method is described. The method includes receiving DDR memory channel signals from a motherboard through a larger DIMM motherboard connector. The method includes routing the signals to one of first and second smaller form factor connectors. The method includes sending the DDR memory channel signals to a DIMM that is connected to the one of the first and second smaller form factor connectors.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: November 5, 2019
    Assignee: Intel Corporation
    Inventors: Xiang Li, Yunhui Chu, Jun Liao, George Vergis, James A. McCall, Charles C. Phares, Konika Ganguly, Qin Li
  • Patent number: 10426381
    Abstract: Switchable grounded terminal loads are built into, or otherwise coupled to, connectors on motherboards and control devices. The terminal loads are coupled to the bus termination at the connector when the connector is “stuffed” (connected to a mating connector). The switchable grounded terminal loads replace dummy connectors in preventing empty “unstuffed” connectors from increasing error risks on active channels.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: October 1, 2019
    Assignee: INTEL CORPORATION
    Inventors: Yunhui Chu, Charles C. Phares, John M. Lynch
  • Publication number: 20190288421
    Abstract: Embodiments may relate to a connector. The connector may include a plurality of connector pins that are to communicatively couple an element of a printed circuit board (PCB) with an element of an electronic device when the element of the PCB and the element of the electronic device are coupled with the connector. The connector may also include an active circuit that is communicatively coupled with a pin of the plurality of pins. The active circuit may be configured to match an impedance of the element of the PCB with an impedance of the element of the electronic device. Other embodiments may be described or claimed.
    Type: Application
    Filed: June 4, 2019
    Publication date: September 19, 2019
    Applicant: Intel Corporation
    Inventors: Jong-Ru Guo, Yunhui Chu, Jun Liao, Kai Xiao, Jingbo Li, Yuanhong Zhao, Mo Liu, Beomtaek Lee, James A. McCall, Jaejin Lee, Xiaoning Ye, Zuoguo Wu, Xiang Li
  • Patent number: 10262599
    Abstract: In some examples, a display includes a plurality of display backlight groups, and one or more controller to determine one or more one-dimensional backlight group brightness level adjustments, to determine one or more two-dimensional backlight group brightness level adjustments, and to adjust a brightness of one or more of the backlight groups in response to content of a display image.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: April 16, 2019
    Assignee: Intel Corporation
    Inventors: John Lang, Yunhui Chu, Yanli Zhang, Zhiming J. Zhuang
  • Publication number: 20190102331
    Abstract: A method is described. The method includes receiving DDR memory channel signals from a motherboard through a larger DIMM motherboard connector. The method includes routing the signals to one of first and second smaller form factor connectors. The method includes sending the DDR memory channel signals to a DIMM that is connected to the one of the first and second smaller form factor connectors.
    Type: Application
    Filed: September 29, 2017
    Publication date: April 4, 2019
    Inventors: Xiang LI, Yunhui CHU, Jun LIAO, George VERGIS, James A. McCALL, Charles C. PHARES, Konika GANGULY, Qin LI
  • Publication number: 20190045622
    Abstract: An apparatus is described. The apparatus includes a semiconductor chip having cross-talk noise cancellation circuitry disposed between a disturber trace and a trace to be protected from cross-talk noise emanating from the disturber trace. The trace is to be coupled to a receiver disposed on a different semiconductor chip.
    Type: Application
    Filed: November 17, 2017
    Publication date: February 7, 2019
    Inventors: Jun LIAO, Zhen ZHOU, James A. McCALL, Jong-Ru GUO, Xiang LI, Yunhui CHU, Zuoguo WU
  • Publication number: 20190045632
    Abstract: Various aspects are related to a connector, e.g., for connecting two boards with one another. The connector may include a housing and a plurality of pins. The housing may include a first housing surface and a second housing surface opposite the first housing surface. Each pin of the plurality of pins may include a first portion protruding arcuately from the first housing surface and a second portion protruding arcuately from the second housing surface.
    Type: Application
    Filed: August 1, 2018
    Publication date: February 7, 2019
    Inventors: Xiang Li, Jun Liao, Yunhui CHU, George Vergis, Chong Zhao
  • Publication number: 20190044289
    Abstract: A shielded SODIMM system for reducing RF emissions of a SODIMM connector is disclosed herein. SODIMM connector RFI presently interferes with connectivity and is also an obstacle for higher speed memory applications. The shielded SODIMM system includes a SODIMM connector that is at least partially housed by a SODIMM connector shield, to partially and/or substantially reduce or block RF emissions from the SODIMM connector. The SODIMM connector shield is at least partially conductive and is coupled to landing pads on a surface of a motherboard printed circuit board (“PCB”). The landing pads of the motherboard PCB that are coupled to the SODIMM connector shield are coupled to ground, which grounds the SODIMM connector shield. Grounding the SODIMM connector shield that at least partially houses the SODIMM connector reduces RF emissions from the SODIMM connector during information transfer operations.
    Type: Application
    Filed: February 20, 2018
    Publication date: February 7, 2019
    Applicant: Intel Corporation
    Inventors: XIANG LI, JAEJIN LEE, JUN LIAO, HAO-HAN HSU, GEORGE VERGIS, YUN LING, DONG-HO HAN, YUNHUI CHU
  • Publication number: 20180277046
    Abstract: In some examples, a display includes a plurality of display backlight groups, and one or more controller to determine one or more one-dimensional backlight group brightness level adjustments, to determine one or more two-dimensional backlight group brightness level adjustments, and to adjust a brightness of one or more of the backlight groups in response to content of a display image.
    Type: Application
    Filed: March 24, 2017
    Publication date: September 27, 2018
    Inventors: John Lang, Yunhui Chu, Yanli Zhang, Zhiming J. Zhuang
  • Patent number: 10084620
    Abstract: Aspects of the embodiments are directed to a data transmission receiver that includes a neural network circuit for resolving a received bit value. The data transmission receiver can be coupled to a data transmitter by a high speed data link. The neural network circuit can sample a bit value at multiple locations across the bit's unit interval. The neural network circuit can also sample bit values for neighboring bits to the interested bit at multiple sampling locations across unit intervals for the neighboring bits. The neural network circuit can determine the value of the interested bit from the samples of the waveform.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: September 25, 2018
    Assignee: Intel Corporation
    Inventors: Yunhui Chu, Fan Chen, John Lang, Charles Phares
  • Publication number: 20180254928
    Abstract: Aspects of the embodiments are directed to a data transmission receiver that includes a neural network circuit for resolving a received bit value. The data transmission receiver can be coupled to a data transmitter by a high speed data link. The neural network circuit can sample a bit value at multiple locations across the bit's unit interval. The neural network circuit can also sample bit values for neighboring bits to the interested bit at multiple sampling locations across unit intervals for the neighboring bits. The neural network circuit can determine the value of the interested bit from the samples of the waveform.
    Type: Application
    Filed: March 1, 2017
    Publication date: September 6, 2018
    Applicant: Intel Corporation
    Inventors: Yunhui Chu, Fan Chen, John Lang, Charles Phares
  • Patent number: 9941643
    Abstract: Switchable grounded terminal loads are built into, or otherwise coupled to, connectors on motherboards and control devices. The terminal loads are coupled to the bus termination at the connector when the connector is “stuffed” (connected to a mating connector). The switchable grounded terminal loads replace dummy connectors in preventing empty “unstuffed” connectors from increasing error risks on active channels.
    Type: Grant
    Filed: December 26, 2015
    Date of Patent: April 10, 2018
    Assignee: Intel Corporation
    Inventors: Yunhui Chu, Charles C. Phares, John M. Lynch