Patents by Inventor Yun-Ki Choi
Yun-Ki Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12199016Abstract: A semiconductor device includes a substrate provided with an integrated circuit and a contact, an interlayer dielectric layer covering the integrated circuit and the contact, a through electrode penetrating the substrate and the interlayer dielectric layer, a first intermetal dielectric layer on the interlayer dielectric layer, and first and second wiring patterns in the first intermetal dielectric layer. The first wiring pattern includes a first conductive pattern on the through electrode, and a first via penetrating the first intermetal dielectric layer and connecting the first conductive pattern to the through electrode. The second wiring pattern includes a second conductive pattern on the contact, and a second via penetrating the first intermetal dielectric layer and connecting the second conductive pattern to the contact. A first width in a first direction of the first via is greater than a second width in the first direction of the second via.Type: GrantFiled: December 5, 2023Date of Patent: January 14, 2025Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Shaofeng Ding, Jeong Hoon Ahn, Yun Ki Choi
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Publication number: 20250014968Abstract: A semiconductor device includes a substrate provided with an integrated circuit and a contact, an interlayer dielectric layer covering the integrated circuit and the contact, a through electrode penetrating the substrate and the interlayer dielectric layer, a first intermetal dielectric layer on the interlayer dielectric layer, and first and second wiring patterns in the first intermetal dielectric layer. The first wiring pattern includes a first conductive pattern on the through electrode, and a first via penetrating the first intermetal dielectric layer and connecting the first conductive pattern to the through electrode. The second wiring pattern includes a second conductive pattern on the contact, and a second via penetrating the first intermetal dielectric layer and connecting the second conductive pattern to the contact. A first width in a first direction of the first via is greater than a second width in the first direction of the second via.Type: ApplicationFiled: September 18, 2024Publication date: January 9, 2025Inventors: SHAOFENG DING, JEONG HOON AHN, YUN KI CHOI
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Publication number: 20250006594Abstract: A semiconductor device includes a substrate provided with an integrated circuit and a contact, an interlayer dielectric layer covering the integrated circuit and the contact, a through electrode penetrating the substrate and the interlayer dielectric layer, a first intermetal dielectric layer on the interlayer dielectric layer, and first and second wiring patterns in the first intermetal dielectric layer. The first wiring pattern includes a first conductive pattern on the through electrode, and a first via penetrating the first intermetal dielectric layer and connecting the first conductive pattern to the through electrode. The second wiring pattern includes a second conductive pattern on the contact, and a second via penetrating the first intermetal dielectric layer and connecting the second conductive pattern to the contact. A first width in a first direction of the first via is greater than a second width in the first direction of the second via.Type: ApplicationFiled: September 16, 2024Publication date: January 2, 2025Inventors: SHAOFENG DING, JEONG HOON AHN, YUN KI CHOI
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Publication number: 20240234490Abstract: A semiconductor device includes a semiconductor substrate including a connection region, a pair of epitaxial patterns provided at the semiconductor substrate, a capacitor disposed between the pair of epitaxial patterns, a middle connection layer on the capacitor, an interconnection layer on the middle connection layer, and a through-via provided under the interconnection layer and penetrating the connection region of the semiconductor substrate. The capacitor includes an upper portion of the semiconductor substrate between the pair of epitaxial patterns, a metal electrode on the upper portion of the semiconductor substrate, and a dielectric pattern disposed between the upper portion of the semiconductor substrate and the metal electrode. The through-via is connected to the capacitor through the interconnection layer and the middle connection layer.Type: ApplicationFiled: March 21, 2024Publication date: July 11, 2024Inventors: SHAOFENG DING, JEONG HOON AHN, YUN KI CHOI
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Patent number: 12034140Abstract: According to an embodiment of the present disclosure, a battery module includes: a cartridge including an accommodation space therein; a plurality of battery cells placed in the accommodation space; a cooling unit configured to cool the battery cells; and a heat exchange unit configured to exchange heat with the cooling unit, wherein the heat exchange unit includes: a heat exchange chamber having an inner space; a lower cooling flow path located in the heat exchange chamber and through which a cooling fluid flows; an upper cooling flow path located above the lower cooling flow path and through which the cooling fluid supplied from the lower cooling flow path flows; and a connection flow path configured to supply the cooling fluid flowing in the lower cooling flow path to the upper cooling flow path.Type: GrantFiled: January 16, 2017Date of Patent: July 9, 2024Assignee: LG ENERGY SOLUTION, LTD.Inventors: Sang-Il Son, Ha-Neul Yoo, Yun-Ki Choi, Jong-Soo Ha
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Patent number: 12014935Abstract: The method of manufacturing an interposer includes providing a substrate including a first region and a second region adjacent to the first region, forming a first mold structure on the substrate, forming a photoresist layer on the first mold structure, forming a first transfer pattern over the photoresist layer on the first region, using a first photomask, forming a second transfer pattern over the photoresist layer on the second region, using the first photomask, forming a mask pattern on the first mold structure, using the first transfer pattern and the second transfer pattern and forming a first trench and a second trench in the first mold structure, using the mask pattern, the first trench being formed in the first region, and the second trench being formed in the second region.Type: GrantFiled: May 14, 2020Date of Patent: June 18, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Shaofeng Ding, Jeong Hoon Ahn, Yun Ki Choi
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Publication number: 20240164081Abstract: A semiconductor device includes a substrate including a logic cell region and a connection region, a dummy transistor on the connection region, an intermediate connection layer on the dummy transistor, the intermediate connection layer including a connection pattern electrically connected to the dummy transistor, a first metal layer on the intermediate connection layer, an etch stop layer between the intermediate connection layer and the first metal layer, the etch stop layer covering a top surface of the connection pattern, and a penetration contact extended from the first metal layer toward a bottom surface of the substrate penetrating the connection region.Type: ApplicationFiled: January 5, 2024Publication date: May 16, 2024Applicant: Samsung Electronics Co., Ltd.Inventors: Shaofeng DING, Jeong Hoon AHN, Yun Ki CHOI
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Patent number: 11961882Abstract: A semiconductor device includes a semiconductor substrate including a connection region, a pair of epitaxial patterns provided at the semiconductor substrate, a capacitor disposed between the pair of epitaxial patterns, a middle connection layer on the capacitor, an interconnection layer on the middle connection layer, and a through-via provided under the interconnection layer and penetrating the connection region of the semiconductor substrate. The capacitor includes an upper portion of the semiconductor substrate between the pair of epitaxial patterns, a metal electrode on the upper portion of the semiconductor substrate, and a dielectric pattern disposed between the upper portion of the semiconductor substrate and the metal electrode. The through-via is connected to the capacitor through the interconnection layer and the middle connection layer.Type: GrantFiled: September 13, 2021Date of Patent: April 16, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Shaofeng Ding, Jeong Hoon Ahn, Yun Ki Choi
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Publication number: 20240106916Abstract: The present invention relates to a device and method for implementing dynamic-service-oriented communication between vehicle applications on an AUTomotive Open System ARchitecture (AUTOSAR) adaptive platform (AP). A machine including an electronic control unit (ECU) to which the portable operating system interface (POSIX) operating system (OS) is ported and implementing dynamic-service-oriented communication between vehicle applications on an AUTOSAR AP includes a skeleton which is an application for providing a service on the platform, a proxy which is an application using the service on the platform, and a service communication management (CM) which is an application for brokering service-oriented communication between vehicle applications on the platform.Type: ApplicationFiled: September 29, 2021Publication date: March 28, 2024Applicant: POPCORNSAR CO., LTD.Inventors: Yun Ki CHOI, Yong Ho LEE, Won Seok CHOI, Kap Hyun KIM
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Publication number: 20240105556Abstract: A semiconductor device includes a substrate provided with an integrated circuit and a contact, an interlayer dielectric layer covering the integrated circuit and the contact, a through electrode penetrating the substrate and the interlayer dielectric layer, a first intermetal dielectric layer on the interlayer dielectric layer, and first and second wiring patterns in the first intermetal dielectric layer. The first wiring pattern includes a first conductive pattern on the through electrode, and a first via penetrating the first intermetal dielectric layer and connecting the first conductive pattern to the through electrode. The second wiring pattern includes a second conductive pattern on the contact, and a second via penetrating the first intermetal dielectric layer and connecting the second conductive pattern to the contact. A first width in a first direction of the first via is greater than a second width in the first direction of the second via.Type: ApplicationFiled: December 5, 2023Publication date: March 28, 2024Inventors: SHAOFENG DING, JEONG HOON AHN, YUN KI CHOI
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Patent number: 11876038Abstract: A semiconductor device includes a substrate provided with an integrated circuit and a contact, an interlayer dielectric layer covering the integrated circuit and the contact, a through electrode penetrating the substrate and the interlayer dielectric layer, a first intermetal dielectric layer on the interlayer dielectric layer, and first and second wiring patterns in the first intermetal dielectric layer. The first wiring pattern includes a first conductive pattern on the through electrode, and a first via penetrating the first intermetal dielectric layer and connecting the first conductive pattern to the through electrode. The second wiring pattern includes a second conductive pattern on the contact, and a second via penetrating the first intermetal dielectric layer and connecting the second conductive pattern to the contact. A first width in a first direction of the first via is greater than a second width in the first direction of the second via.Type: GrantFiled: September 8, 2021Date of Patent: January 16, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Shaofeng Ding, Jeong Hoon Ahn, Yun Ki Choi
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Patent number: 11871553Abstract: A semiconductor device includes a substrate including a logic cell region and a connection region, a dummy transistor on the connection region, an intermediate connection layer on the dummy transistor, the intermediate connection layer including a connection pattern electrically connected to the dummy transistor, a first metal layer on the intermediate connection layer, an etch stop layer between the intermediate connection layer and the first metal layer, the etch stop layer covering a top surface of the connection pattern, and a penetration contact extended from the first metal layer toward a bottom surface of the substrate penetrating the connection region.Type: GrantFiled: September 14, 2021Date of Patent: January 9, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Shaofeng Ding, Jeong Hoon Ahn, Yun Ki Choi
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Patent number: 11798883Abstract: A semiconductor device includes an integrated circuit (IC) and an interlayer dielectric layer on the substrate, a contact through the interlayer dielectric layer and electrically connected to the IC, a wiring layer on the interlayer dielectric layer with a wiring line electrically connected to the contact, a first passivation layer on the wiring layer, first and second pads on the first passivation layer, and a through electrode through the substrate, the interlayer dielectric layer, the wiring layer, and the first passivation layer to connect to the first pad. The first pad includes a first head part on the first passivation layer, and a protruding part that extends into the first passivation layer from the first head part, the protruding part surrounding a lateral surface of the through electrode in the first passivation layer, and the second pad is connected to the IC through the wiring line and the contact.Type: GrantFiled: November 16, 2021Date of Patent: October 24, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Shaofeng Ding, Jeong Hoon Ahn, Yun Ki Choi
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Publication number: 20230317539Abstract: A semiconductor package includes a circuit board, an interposer structure on the circuit board, a first semiconductor chip and a second semiconductor chip on the interposer structure, the first and the second semiconductor chips electrically connected to the interposer structure and spaced apart from each other, and a mold layer between the first and second semiconductor chips, the mold layer separating the first and second semiconductor chips. A slope of a side wall of the mold layer is constant as the side wall extends away from an upper side of the interposer structure, and an angle defined by a bottom side of the mold layer and the side wall of the mold layer is less than or equal to ninety degrees.Type: ApplicationFiled: November 15, 2022Publication date: October 5, 2023Applicant: Samsung Electronics Co., Ltd.Inventors: Bo In NOH, Jeong Hoon AHN, Yun Ki CHOI
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Publication number: 20230260893Abstract: A semiconductor device includes a semiconductor substrate having a first surface and a second surface opposite to the first surface; a transistor provided on the first surface of the semiconductor substrate; a power rail provided on the first surface of the semiconductor substrate and electrically connected to the transistor; first and second lower interconnection lines provided on the second surface of the semiconductor substrate and spaced apart from each other in a first direction perpendicular to the second surface of the semiconductor substrate; a penetration via penetrating the semiconductor substrate and connecting a corresponding one of the first and second lower interconnection lines to the power rail; and a capacitor provided between and electrically connected to the first and second lower interconnection lines.Type: ApplicationFiled: October 27, 2022Publication date: August 17, 2023Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: JIHYUNG KIM, JAEHEE OH, JEGWAN HWANG, SHAOFENG DING, WON JI PARK, JEONG HOON AHN, YUN KI CHOI
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Patent number: 11728311Abstract: A semiconductor device includes an interposer substrate and at least one die mounted on the interposer substrate. The interposer substrate includes a semiconductor substrate having a first surface and a second surface opposite to the first surface, an interlayer insulating layer on the first surface of the semiconductor substrate, a capacitor in a hole penetrating the interlayer insulating layer, an interconnection layer on the interlayer insulating layer, and a through-via extending from the interconnection layer toward the second surface of the semiconductor substrate in a vertical direction that is perpendicular to the first surface of the semiconductor substrate. The capacitor includes a sequential stack of a first electrode, a first dielectric layer, a second electrode, a second dielectric layer and a third electrode. A bottom of the hole is distal from the second surface of the semiconductor substrate in relation to the first surface of the semiconductor substrate.Type: GrantFiled: March 1, 2021Date of Patent: August 15, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Shaofeng Ding, Jeong Hoon Ahn, Yun Ki Choi
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Publication number: 20230230944Abstract: A semiconductor package includes a second semiconductor chip disposed on a first semiconductor chip. The first semiconductor chip includes a first semiconductor substrate, a through via, and a lower pad disposed on the through via. The lower pad includes a first segment and a second segment connected thereto. The first segment overlaps the through via. The second segment is disposed on an edge region of the first segment. The second segment has an annular shape. The second semiconductor chip includes a second semiconductor substrate, an upper pad disposed on a bottom surface of the second semiconductor substrate, and a connection terminal disposed between the upper and lower pads. The second segment at least partially surrounds a lateral surface of the upper pad. A level of a top surface of the second segment is higher than that of an uppermost portion of the connection terminal.Type: ApplicationFiled: October 4, 2022Publication date: July 20, 2023Inventors: Boin NOH, Jeong Hoon AHN, Yun Ki CHOI
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Publication number: 20230131382Abstract: Disclosed is a three-dimensional integrated circuit structure including an active device die and a capacitor die stacked on the logic die. The active device die includes: a first substrate including a front side and a back side that are opposite to each other; a power delivery network on the back side of the first substrate; a device layer on the front side of the first substrate; a first wiring layer on the device layer; and a through contact that vertically extends from the power delivery network to the first wiring layer.Type: ApplicationFiled: June 17, 2022Publication date: April 27, 2023Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Shaofeng DING, Jihyung KIM, Won Ji PARK, Jeong Hoon AHN, Jaehee OH, Yun Ki CHOI
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Publication number: 20230099844Abstract: Provided is a semiconductor package including a first chip substrate including a first surface and a second surface, a through via passing through the first chip substrate, an upper passivation layer including a trench on the second surface of the first chip substrate, the trench exposing at least a portion of the second surface of the first chip substrate, an upper pad electrically connected with the through via on the trench, a second chip substrate including a third surface and a fourth surface, a lower pad electrically connected to the second chip substrate on the third surface of the second chip substrate, and a connection bump electrically connecting the upper pad with the lower pad and contacting the lower pad, wherein a width of the connection bump increases as the connection bump becomes farther away from the first surface of the first chip substrate.Type: ApplicationFiled: June 2, 2022Publication date: March 30, 2023Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yong Ho KIM, Woo Jin JANG, Jeong Hoon AHN, Yun Ki CHOI
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Interposer structure, semiconductor package comprising the same, and method for fabricating the same
Patent number: 11538747Abstract: Provided is an interposer structure. The interposer structure comprises an interposer substrate, an interlayer insulating film which covers a top surface of the interposer substrate, a capacitor structure in the interlayer insulating film and a wiring structure including a first wiring pattern and a second wiring pattern spaced apart from the first wiring pattern, on the interlayer insulating film, wherein the capacitor structure includes an upper electrode connected to the first wiring pattern, a lower electrode connected to the second wiring pattern, and a capacitor dielectric film between the upper electrode and the lower electrode.Type: GrantFiled: May 22, 2020Date of Patent: December 27, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Shaofeng Ding, Jae June Jang, Jeong Hoon Ahn, Yun Ki Choi