Abstract: A compound, as represented by formula I, as a TLR7 agonist, a method for preparing the compound, and the use of the compound in treating diseases mediated by the TLR7 agonist are provided. Studies on the activity of a human-derived receptor, a TLR7 agonist, show that compounds have a strong agonistic effect on the human-derived receptor, TLR7, and can be used as a foreground compound for treating diseases mediated by the TLR7 agonist.

Abstract: A display substrate and a manufacturing method and a display device are provided. The display substrate includes: a base substrate, a first insulation layer, a first electrode pattern, a connecting electrode pattern, a second electrode, a light-emitting functional layer, and a first filling layer. The second electrode is connected with the connecting electrode pattern, the second electrode and the first electrode pattern are spaced apart from each other. The light-emitting functional layer is located between the first electrode pattern and the second electrode. The first filling layer is located between the connecting electrode pattern and the first electrode pattern. The first filling layer and the light-emitting functional layer are different layers; a portion of the first insulation layer that is located between the first electrode pattern and the connecting electrode pattern has a groove, and the first filling layer is at least partially located in the groove.

Abstract: A method of fabricating an integrated circuit includes etching trenches in a first surface of a semiconductor layer. A trench dielectric layer is formed over the first surface and over bottoms and sidewalls of the trenches and a doped polysilicon layer is formed over the trench dielectric layer and within the trenches. The doped polysilicon layer is patterned to form a polysilicon bridge that connects to the polysilicon within the filled trenches and a blanket implant of a first dopant is directed to the polysilicon bridge and to the first surface. The blanket implant forms a contact region extending from the first surface into the semiconductor layer.

Abstract: An integrated circuit includes first and second trenches in a semiconductor substrate and a semiconductor mesa between the first and second trenches. A source region having a first conductivity type and a body region having an opposite second conductivity type are located within the semiconductor mesa. A trench shield is located within the first trench, and a gate electrode is over the trench shield between first and second sidewalls of the first trench. A gate dielectric is on a sidewall of the first trench between the gate electrode and the body region, and a pre-metal dielectric (PMD) layer is over the gate electrode. A gate contact through the PMD layer touches the gate electrode between the first and second sidewalls, and a trench shield contact through the PMD layer touches the trench shield between the first and second sidewalls.

Abstract: A method of fabricating an integrated circuit includes etching trenches in a first surface of a semiconductor layer. A trench dielectric layer is formed over the first surface and over bottoms and sidewalls of the trenches and a doped polysilicon layer is formed over the trench dielectric layer and within the trenches. The doped polysilicon layer is patterned to form a polysilicon bridge that connects to the polysilicon within the filled trenches and a blanket implant of a first dopant is directed to the polysilicon bridge and to the first surface. The blanket implant forms a contact region extending from the first surface into the semiconductor layer.

Abstract: A method for constructing a steel sheet pile cofferdam is provided, including: step S1, determining a construction area of the steel sheet pile cofferdam; step S2, piling steel casings, and welding guide frame brackets to the steel casings, the guide frame brackets are connected with a guide frame and limiting clamp plates; step S3, piling steel sheet piles by relying on the guide frame; step S4, pouring subsealing concrete at a bottom of the steel sheet pile cofferdam; step S5, arranging purlins and internal supports within the steel sheet pile cofferdam; step S6, perform a secondary subsealing at the bottom of the steel sheet pile cofferdam; step S7, pumping water within the steel sheet pile cofferdam through a pump and pouring to form a bearing platform on the subsealing concrete; step S8, removing the steel sheet pile cofferdam after the bearing platform is formed.

Abstract: A semiconductor device has a semiconductor material in a substrate. The semiconductor device has an MOS transistor. A trench in the substrate extends from a top surface of the substrate) into the semiconductor material. A shield is disposed in the trench. The shield has a contact portion which extends toward a top surface of the trench. A gate of the MOS transistor is disposed in the trench over the shield. The gate is electrically isolated from the shield. The gate is electrically isolated from the contact portion of the shield by a shield isolation layer which covers an angled surface of the contact portion extending toward the top of the trench. Methods of forming the semiconductor device are disclosed.

Abstract: A hydrolysis method for tert-butyl ester in gadolinium-based contrast agent comprises hydrolyzing the tert-butyl ester with a catalyst. The preparation method of the catalyst comprises the following steps: subjecting zirconia and titanium tetrachloride to reaction in the presence of sulfuric acid and water at 60° C. to 90° C. until solids are dissolved, adding silica to perform reaction for 1 to 5 h, filtering to obtain solids, washing and calcining the solids. This hydrolysis method does not introduce other substances that are difficult to remove, such as acids, and provides high hydrolysis efficiency and high purity of the obtained product.

Abstract: A method for constructing a steel sheet pile cofferdam is provided, including: step S1, determining a construction area of the steel sheet pile cofferdam; step S2, piling steel casings, and welding guide frame brackets to the steel casings, the guide frame brackets are connected with a guide frame and limiting clamp plates; step S3, piling steel sheet piles by relying on the guide frame; step S4, pouring subsealing concrete at a bottom of the steel sheet pile cofferdam; step S5, arranging purlins and internal supports within the steel sheet pile cofferdam; step S6, perform a secondary subsealing at the bottom of the steel sheet pile cofferdam; step S7, pumping water within the steel sheet pile cofferdam through a pump and pouring to form a bearing platform on the subsealing concrete; step S8, removing the steel sheet pile cofferdam after the bearing platform is formed.

Abstract: In a described example, a method of forming a capacitor includes forming a doped polysilicon layer over a semiconductor substrate. The method also includes forming a dielectric layer on the doped polysilicon layer. The method also includes forming an undoped polysilicon layer on the dielectric layer.

Abstract: A method of fabricating an integrated circuit includes etching trenches in a first surface of a semiconductor layer. A trench dielectric layer is formed over the first surface and over bottoms and sidewalls of the trenches and a doped polysilicon layer is formed over the trench dielectric layer and within the trenches. The doped polysilicon layer is patterned to form a polysilicon bridge that connects to the polysilicon within the filled trenches and a blanket implant of a first dopant is directed to the polysilicon bridge and to the first surface. The blanket implant forms a contact region extending from the first surface into the semiconductor layer.

Abstract: In a semiconductor process, a seamless tungsten plug is formed in an inter-layer dielectric by forming the inter-layer dielectric from multiple oxide layers having different wet etch rates, from lowest wet-etch rate for the lowest layer to highest wet-etch rate for the highest layer, forming a hole or trench in the inter-layer dielectric using a dry etch process, reconfiguring the hole or trench to have sloped side walls by performing a wet etch step, and filling the hole or trench with tungsten and etching back the tungsten to form a seamless tungsten plug.

Abstract: The present invention discloses an in-place non-contact detection method for a shaft workpiece. The method includes: establishing a detection system, calibrating the detection system and establishing a detection coordinate system; analyzing a pose of a workpiece in the detection system to establish a coordinate system of a workpiece clamping device; controlling the workpiece clamping device of a shaft workpiece processing machine tool to rotate, continuously acquiring data by a linear laser measuring instrument, and calculating and analyzing the acquired data to obtain an ideal reference axis of the shaft workpiece; continuously acquiring data of a detection part, and calculating and analyzing the acquired data to obtain actual machining precision of runout of a shaft neck of a camshaft; and continuously acquiring data of the detection part, and calculating and analyzing the acquired data to obtain machining precision of coaxiality of the shaft workpiece.

Abstract: A method (200) of fabricating a semiconductor device includes etching (205) a group of trenches in a semiconductor surface layer of a substrate. The group of trenches includes an outermost trench that has a first width and remaining trenches of the group of trenches have a second width that is less than the first width. The outermost trench is formed at an edge of the group of trenches. A dielectric liner is formed (210) in the group of trenches and the dielectric liner is etched (215) in an upper portion of the group of trenches to remove a partial thickness of the dielectric liner. A full thickness of the dielectric liner is maintained in a lower portion of the group of trenches. The group of trenches is filled (220) with a polysilicon layer.

Abstract: A semiconductor device has a semiconductor material in a substrate. The semiconductor device has an MOS transistor. A trench in the substrate extends from a top surface of the substrate) into the semiconductor material. A shield is disposed in the trench. The shield has a contact portion which extends toward a top surface of the trench. A gate of the MOS transistor is disposed in the trench over the shield. The gate is electrically isolated from the shield. The gate is electrically isolated from the contact portion of the shield by a shield isolation layer which covers an angled surface of the contact portion extending toward the top of the trench. Methods of forming the semiconductor device are disclosed.

Abstract: A semiconductor device, and methods of forming the same. In one example, the semiconductor device includes a trench in a substrate having a top surface, and a shield within the trench. The semiconductor device also includes a shield liner between a sidewall of the trench and the shield, and a lateral insulator over the shield contacting the shield liner. The semiconductor device also includes a gate dielectric layer on an exposed sidewall of the trench between the lateral insulator and the top surface. The lateral insulator may have a minimum thickness at least two times thicker than a maximum thickness of the gate dielectric layer.

Abstract: A semiconductor device has a semiconductor material in a substrate. The semiconductor device has an MOS transistor. A trench in the substrate extends from a top surface of the substrate) into the semiconductor material. A shield is disposed in the trench. The shield has a contact portion which extends toward a top surface of the trench. A gate of the MOS transistor is disposed in the trench over the shield. The gate is electrically isolated from the shield. The gate is electrically isolated from the contact portion of the shield by a shield isolation layer which covers an angled surface of the contact portion extending toward the top of the trench. Methods of forming the semiconductor device are disclosed.

Abstract: A method (200) of fabricating a semiconductor device includes etching (205) a group of trenches in a semiconductor surface layer of a substrate. The group of trenches includes an outermost trench that has a first width and remaining trenches of the group of trenches have a second width that is less than the first width. The outermost trench is formed at an edge of the group of trenches. A dielectric liner is formed (210) in the group of trenches and the dielectric liner is etched (215) in an upper portion of the group of trenches to remove a partial thickness of the dielectric liner. A full thickness of the dielectric liner is maintained in a lower portion of the group of trenches. The group of trenches is filled (220) with a polysilicon layer.

Abstract: A trench capacitor includes a plurality of trenches in a semiconductor substrate. A first polysilicon layer is located within the plurality of trenches and over a top surface of the substrate. The first polysilicon layer is continuous between the plurality of trenches. The trench capacitor further includes a plurality of second polysilicon layers. Each of the second polysilicon layers fills a corresponding trench of the plurality of trenches. The second polysilicon layers each extend to a top surface of the first polysilicon layer.

Abstract: A semiconductor device, and methods of forming the same. In one example, the semiconductor device includes a trench in a substrate having a top surface, and a shield within the trench. The semiconductor device also includes a shield liner between a sidewall of the trench and the shield, and a lateral insulator over the shield contacting the shield liner. The semiconductor device also includes a gate dielectric layer on an exposed sidewall of the trench between the lateral insulator and the top surface. The lateral insulator may have a minimum thickness at least two times thicker than a maximum thickness of the gate dielectric layer.