Abstract: An integrated circuit including a trench in the substrate with a high quality trench oxide grown on the sidewalls and the bottom of the trench where the ratio of the thickness of the high quality trench oxide formed on the sidewalls to the thickness formed on the bottom is less than 1.2. An integrated circuit including a trench with high quality oxide is formed by first growing a sacrificial oxide in dilute oxygen at a temperature in the range of 1050° C. to 1250° C., stripping the sacrificial oxide, growing high quality oxide in dilute oxygen plus trans 1,2 dichloroethylene at a temperature in the range of 1050° C. to 1250° C., and annealing the high quality oxide in an inert ambient at a temperature in the range of 1050° C. to 1250° C.

Abstract: A method of fabricating a semiconductor device includes etching a semiconductor substrate having a top surface to form a trench having sidewalls and a bottom surface that extends from the top surface into the semiconductor substrate. A dielectric liner of a first dielectric material is formed on the bottom surface and sidewalls of the trench to line the trench. A second dielectric layer of a second dielectric material is deposited to at least partially fill the trench. The second dielectric layer is partially etched to selectively remove the second dielectric layer from an upper portion of the trench while preserving the second dielectric layer on a lower portion of the trench. The trench is filled with a fill material which provides an electrical conductivity that is at least that of a semiconductor.

Abstract: A planar gate power MOSFET includes a substrate having a semiconductor surface doped a first conductivity type, a plurality of transistor cells (cells) including a first cell and at least a second cell each having a gate stack over a body region. A trench has an aspect ratio of >3 extending down from a top side of the semiconductor surface between the gate stacks providing a source contact (SCT) from a source doped a second conductivity type to the substrate. A field plate (FP) is over the gate stacks that provides a liner for the trench. The trench has a refractory metal or platinum-group metal (PGM) metal filler within. A drain doped the second conductivity type is in the semiconductor surface on a side of the gate stacks opposite the trench.

Abstract: Systems and methods for rotating shield brachytherapy. In an aspect, some of the systems and methods can be used to facilitate shield selection for use in rotating shield brachytherapy. In an aspect, the invention is a shielded needle or catheter system with a rotational controller for delivering radioisotope-based interstitial rotating shield brachytherapy (I-RSBT). In an aspect, the catheter system can utilize paddle-based RSBT. Further provided are methods and systems for helical RSBT.

Abstract: A method of fabricating a semiconductor device includes etching a semiconductor substrate having a top surface to form a trench having sidewalls and a bottom surface that extends from the top surface into the semiconductor substrate. A dielectric liner of a first dielectric material is formed on the bottom surface and sidewalls of the trench to line the trench. A second dielectric layer of a second dielectric material is deposited to at least partially fill the trench. The second dielectric layer is partially etched to selectively remove the second dielectric layer from an upper portion of the trench while preserving the second dielectric layer on a lower portion of the trench. The trench is filled with a fill material which provides an electrical conductivity that is at least that of a semiconductor.

Abstract: A method, apparatus, and program product generate an estimation of an incremental recovery for an Enhanced Oil Recovery (EOR) process performed on a naturally-fractured reservoir by classifying the naturally-fractured reservoir based upon a set of reservoir properties associated with the naturally-fractured reservoir, and generating an estimation of the incremental recovery for at least one EOR process based on the classification of the naturally-fractured reservoir.

Abstract: An integrated circuit including a trench in the substrate with a high quality trench oxide grown on the sidewalls and the bottom of the trench where the ratio of the thickness of the high quality trench oxide formed on the sidewalls to the thickness formed on the bottom is less than 1.2. An integrated circuit including a trench with high quality oxide is formed by first growing a sacrificial oxide in dilute oxygen at a temperature in the range of 1050° C. to 1250° C., stripping the sacrificial oxide, growing high quality oxide in dilute oxygen plus trans 1,2 dichloroethylene at a temperature in the range of 1050° C. to 1250° C., and annealing the high quality oxide in an inert ambient at a temperature in the range of 1050° C. to 1250° C.

Abstract: A method of fabricating a FET includes forming a gate on the surface of a substrate. A trench contact extends between a first region located proximate the surface of the substrate and a second region located below the first region is formed in the surface. The surface of the substrate is coated with a conductive material, wherein the conductive material at least partially covers the gate and lines the trench contact to electrically connect the first region and the second region. A void remains in the trench contact. A dielectric material is applied to the conductive material, wherein the dielectric material at least partially fills the void in the trench contact. At least a portion of the conductive material is etched from the gate.

Abstract: An semiconductor device with a low resistance sinker contact wherein the low resistance sinker contact is etched through a first doped layer and is etched into a second doped layer and wherein the first doped layer overlies the second doped layer and wherein the second doped layer is more heavily doped that the first doped layer and wherein the low resistance sinker contact is filled with a metallic material.

Abstract: An integrated circuit including a trench in the substrate with a high quality trench oxide grown on the sidewalls and the bottom of the trench where the ratio of the thickness of the high quality trench oxide formed on the sidewalls to the thickness formed on the bottom is less than 1.2. An integrated circuit including a trench with high quality oxide is formed by first growing a sacrificial oxide in dilute oxygen at a temperature in the range of 1050° C. to 1250° C., stripping the sacrificial oxide, growing high quality oxide in dilute oxygen plus trans 1,2 dichloroethylene at a temperature in the range of 1050° C. to 1250° C., and annealing the high quality oxide in an inert ambient at a temperature in the range of 1050° C. to 1250° C.

Abstract: A method of fabricating a FET includes forming a gate on the surface of a substrate. A trench contact extends between a first region located proximate the surface of the substrate and a second region located below the first region is formed in the surface. The surface of the substrate is coated with a conductive material, wherein the conductive material at least partially covers the gate and lines the trench contact to electrically connect the first region and the second region. A void remains in the trench contact. A dielectric material is applied to the conductive material, wherein the dielectric material at least partially fills the void in the trench contact. At least a portion of the conductive material is etched from the gate.

Abstract: An semiconductor device with a low resistance sinker contact wherein the low resistance sinker contact is etched through a first doped layer and is etched into a second doped layer and wherein the first doped layer overlies the second doped layer and wherein the second doped layer is more heavily doped that the first doped layer and wherein the low resistance sinker contact is filled with a metallic material. A method for forming a semiconductor device with a low resistance sinker contact wherein the low resistance sinker contact is etched through a first doped layer and is etched into a second doped layer and wherein the first doped layer overlies the second doped layer and wherein the second doped layer is more heavily doped that the first doped layer and wherein the low resistance sinker contact is filled with a metallic material.

Abstract: A method of fabricating a semiconductor device includes etching a semiconductor substrate having a top surface to form a trench having sidewalls and a bottom surface that extends from the top surface into the semiconductor substrate. A dielectric liner of a first dielectric material is formed on the bottom surface and sidewalls of the trench to line the trench. A second dielectric layer of a second dielectric material is deposited to at least partially fill the trench. The second dielectric layer is partially etched to selectively remove the second dielectric layer from an upper portion of the trench while preserving the second dielectric layer on a lower portion of the trench. The trench is filled with a fill material which provides an electrical conductivity that is at least that of a semiconductor.

Abstract: In an semiconductor process, a seamless tungsten plug is formed in an inter-layer dielectric by forming the inter-layer dielectric from multiple oxide layers having different wet etch rates, from lowest wet-etch rate for the lowest layer to highest wet-etch rate for the highest layer, forming a hole or trench in the inter-layer dielectric using a dry etch process, reconfiguring the hole or trench to have sloped side walls by performing a wet etch step, and filling the hole or trench with tungsten and etching back the tungsten to form a seamless tungsten plug.

Abstract: Systems and methods for rotating shield brachytherapy. In an aspect, some of the systems and methods can be used to facilitate shield selection for use in rotating shield brachytherapy. In an aspect, the invention is a shielded needle or catheter system with a rotational controller for delivering radioisotope-based interstitial rotating shield brachytherapy (I-RSBT), In an aspect, I-RSBT needles can deliver dose distributions that can be non-radially symmetric about each needle, enabling reduced doses to sensitive normal tissues. Further provided are methods and systems for selecting an emission angle for use in S-RSBT and for sequencing the rotating shields. Further provided are methods and system for the multiple application of M-RSBT in a single setting.

Abstract: A method, apparatus, and program product generate an estimation of an incremental recovery for an Enhanced Oil Recovery (EOR) process performed on a naturally-fractured reservoir by classifying the naturally-fractured reservoir based upon a set of reservoir properties associated with the naturally-fractured reservoir, and generating an estimation of the incremental recovery for at least one EOR process based on the classification of the naturally-fractured reservoir.

Abstract: A method of planning a procedure for cleaning a wellbore by injecting a cleaning fluid from a reservoir into the wellbore includes detecting properties and conditions of fluids circulating between the reservoir and the wellbore; preparing a data set from the detected properties and conditions of the fluids circulating between the reservoir and the wellbore; simulating a cleaning operation model of injecting the cleaning fluid into the wellbore based on the data set; determining parameter settings of the simulated cleaning operation model that satisfy prescribed constraints; and producing the procedure for cleaning the wellbore based on the determined parameters. A system for conducting a procedure for cleaning a wellbore includes a sensor unit; a control unit; and a cleanup simulation system.

Abstract: Methods are provided for empirically determining transcription levels of target genes based on the number of cis-acting elements provided in untranslated regulatory regions and for identifying the transcription binding motifs in the 5′ regulatory region of a target gene or gene family.