Abstract: Methods for controlling bevel etch rate of a substrate during plasma processing within a processing chamber includes securing the substrate on a lower electrode within the processing chamber. A power source is provided. A gas mixture is flowed into the processing chamber. A first match arrangement coupled to an upper electrode is adjusted to control current flowing through the upper electrode to change the upper electrode from a grounded state to a floating state. A second match arrangement coupled to a top ring electrode is adjusted to control current flowing through the top ring electrode so as to control plasma formed above a top edge of the substrate. An extension of the upper electrode is lowered during plasma processing so as to minimize a gap between the extension of the upper electrode and the substrate received on the lower electrode, such that the gap is incapable of supporting plasma formed in the processing chamber.

Abstract: Methods of doping semiconductor substrates using deposition of a rare earth metal-containing film such as an yttrium-containing film, and annealing techniques are provided herein. Rare earth metal-containing films are deposited using gas, liquid, or solid precursors without a bias and may be deposited conformally. Some embodiments may involve deposition using a plasma. Substrates may be annealed at temperatures less than about 500° C.

Abstract: A method for forming a junction in a germanium (Ge) layer of a substrate includes arranging the substrate in a processing chamber. The method includes performing a plasma pretreatment on the substrate in the processing chamber for a predetermined pretreatment period using a pretreatment plasma gas mixture including hydrogen gas species. The method includes supplying a doping plasma gas mixture to the processing chamber including a phosphorous (P) gas species and an antimony (Sb) gas species. The method includes striking plasma in the processing chamber for a predetermined doping period. The method includes annealing the substrate during a predetermined annealing period to form the junction in the germanium (Ge) layer.

Abstract: A method for isotropically etching film on a substrate with atomic layer control includes a) providing a substrate including a material selected from a group consisting of silicon (Si), germanium (Ge) and silicon germanium (SiGe). The method includes b) depositing a sacrificial layer on the material in a processing chamber by: cooling a lower portion of the substrate; one of creating or supplying an oxidant-containing plasma in the processing chamber; and increasing a surface temperature of the substrate for a predetermined period using rapid thermal heating while creating or supplying the oxidant-containing plasma in the processing chamber. The method includes c) purging the processing chamber. The method includes d) etching the sacrificial layer and the material by supplying an etch gas mixture and striking plasma in the processing chamber.

Abstract: The embodiments disclosed herein pertain to methods and apparatus for depositing stress compensating layers and sacrificial layers on either the front side or back side of a substrate. In various implementations, back side deposition occurs while the wafer is in a normal front side up orientation. The front/back side deposition may be performed to reduce stress introduced through deposition on the front side of the wafer. The back side deposition may also be performed to minimize back side particle-related problems that occur during post-deposition processing such as photolithography.

Abstract: A lower plasma-exclusion-zone ring for a bevel etcher is provided that is configured to etch a bevel edge of a substrate. The lower plasma-exclusion-zone ring includes a ring-shaped body and a radially-outer stepped surface. The ring-shaped body of the lower plasma-exclusion-zone ring defines an upper surface, a lower surface, a radially inner surface, and a radially outer surface. The radially-outer stepped surface of the lower plasma-exclusion-zone ring extending inwardly into the ring-shaped body between the radially outer surface of the ring-shaped body and the upper surface of the ring-shaped body. The ring-shaped body is made of a material selected from a group consisting of aluminum oxide, aluminum nitride, silicon, silicon carbide, silicon nitride, and yttria.

Abstract: An upper plasma-exclusion-zone ring for a bevel etcher is provided that is configured to etch a bevel edge of a substrate. The upper plasma-exclusion-zone ring includes a ring-shaped body and a radially-inner stepped surface. The ring-shaped body of the upper plasma-exclusion-zone ring defines an upper surface, a lower surface, a radially inner surface, and a radially outer surface. The radially-inner stepped surface of the upper plasma-exclusion-zone ring extends inwardly into the ring-shaped body between the radially inner surface of the ring-shaped body and the lower surface of the ring-shaped body. The ring-shaped body is made of a material selected from a group consisting of aluminum oxide, aluminum nitride, silicon, silicon carbide, silicon nitride, and yttria.

Abstract: A lower electrode plate receives radiofrequency power. A first upper plate is positioned parallel to and spaced apart from the lower electrode plate. A grounded second upper plate is positioned next to the first upper plate. A dielectric support provides support of a workpiece within a region between the lower electrode plate and the first upper plate. A purge gas is supplied at a central location of the first upper plate. A process gas is supplied to a periphery of the first upper plate. The dielectric support positions the workpiece proximate and parallel to the first upper plate, such that the purge gas flows over a top surface of the workpiece so as to prevent the process gas from flowing over the top surface of the workpiece, and so as to cause the process gas to flow around a peripheral edge of the workpiece and below the workpiece.

Abstract: Methods of doping semiconductor substrates using deposition of a rare earth metal-containing film such as an yttrium-containing film, and annealing techniques are provided herein. Rare earth metal-containing films are deposited using gas, liquid, or solid precursors without a bias and may be deposited conformally. Some embodiments may involve deposition using a plasma. Substrates may be annealed at temperatures less than about 500° C.

Abstract: Well-controlled, conformal doping of semiconductor substrates may be achieved by low temperature hydrogen-containing plasma treatment prior to gas phase doping. Substrates doped in this manner may be capped and annealed for thermal drive-in of the dopant. The technique is particularly applicable to the formation of ultrashallow junctions (USJs) in three-dimensional (3D) semiconductor structures, such as FinFET and Gate-All-Around (GAA) devices.

Abstract: The embodiments provide apparatus and methods for removal of etch byproducts, dielectric films and metal films near the substrate bevel edge, and chamber interior to avoid the accumulation of polymer byproduct and deposited films and to improve process yield. In an exemplary embodiment, a plasma processing chamber configured to clean a bevel edge of a substrate is provided. The plasma processing chamber includes a substrate support configured to receive the substrate. The plasma processing chamber also includes a bottom edge electrode surrounding the substrate support. The bottom edge electrode and the substrate support are electrically isolated from one another by a bottom dielectric ring. A surface of the bottom edge electrode facing the substrate is covered by a bottom thin dielectric layer. The plasma processing chamber further includes a top edge electrode surrounding a top insulator plate opposing the substrate support. The top edge electrode is electrically grounded.

Abstract: A method for forming a junction on a substrate includes removing a native oxide layer of a bulk material; doping an outer layer of the bulk material with molecular hydrogen to create a hydrogen-doped outer layer; and nano-doping the hydrogen-doped outer layer using one of boron or phosphorous to a target junction depth to create a nano-doped layer.

Abstract: A method for forming a junction on a substrate includes removing a native oxide layer of a bulk material; doping an outer layer of the bulk material with molecular hydrogen to create a hydrogen-doped outer layer; and nano-doping the hydrogen-doped outer layer using one of boron or phosphorous to a target junction depth to create a nano-doped layer.

Abstract: Methods for controlling bevel etch rate of a substrate during plasma processing within a processing chamber includes securing the substrate on a lower electrode within the processing chamber. A power source is provided. A gas mixture is flowed into the processing chamber. A first match arrangement coupled to an upper electrode is adjusted to control current flowing through the upper electrode to change the upper electrode from a grounded state to a floating state. A second match arrangement coupled to a top ring electrode is adjusted to control current flowing through the top ring electrode so as to control plasma formed above a top edge of the substrate. An extension of the upper electrode is lowered during plasma processing so as to minimize a gap between the extension of the upper electrode and the substrate received on the lower electrode, such that the gap is incapable of supporting plasma formed in the processing chamber.

Abstract: A process chamber includes a wafer support to mount a wafer to be processed in the process chamber, with the wafer having an annular edge exclusion area. A first electrically grounded ring extends in an annular path radially outward of the edge exclusion area and is electrically isolated from the wafer support. A second electrode is configured with a center area opposite to the wafer support. A second electrically grounded ring extends in an annular path radially outward of the second electrode and the edge exclusion area. The second electrically grounded ring is electrically isolated from the center area. An annular mount section has a DC bias ring, and the DC bias ring opposes the edge exclusion area when the wafer is present. A DC control circuit is provided for applying a DC voltage to the DC bias ring.

Abstract: The embodiments provide apparatus and methods for removal of etch byproducts, dielectric films and metal films near the substrate bevel edge, and chamber interior to avoid the accumulation of polymer byproduct and deposited films and to improve process yield. In an exemplary embodiment, a plasma processing chamber configured to clean a bevel edge of a substrate is provided. The plasma processing chamber includes a substrate support configured to receive the substrate. The plasma processing chamber also includes a bottom edge electrode surrounding the substrate support. The bottom edge electrode and the substrate support are electrically isolated from one another by a bottom dielectric ring. A surface of the bottom edge electrode facing the substrate is covered by a bottom thin dielectric layer. The plasma processing chamber further includes a top edge electrode surrounding a top insulator plate opposing the substrate support. The top edge electrode is electrically grounded.

Abstract: An arrangement for controlling bevel etch rate during plasma processing within a processing chamber. The arrangement includes a power source and a gas distribution system. The arrangement also includes a lower electrode, which is configured at least for supporting a substrate. The arrangement further includes a top ring electrode positioned above the substrate and a bottom ring electrode positioned below the substrate. The arrangement yet also includes a first match arrangement coupled to the top ring electrode and configured at least for controlling current flowing through the top ring electrode to control amount of plasma available for etching at least a part of the substrate top edge. The arrangement yet further includes a second match arrangement configured to control the current flowing through the bottom ring electrode to control amount of plasma available for at least etching at least a part of the substrate bottom edge.

Abstract: The embodiments disclosed herein pertain to methods and apparatus for depositing stress compensating layers and sacrificial layers on either the front side or back side of a substrate. In various implementations, back side deposition occurs while the wafer is in a normal front side up orientation. The front/back side deposition may be performed to reduce stress introduced through deposition on the front side of the wafer. The back side deposition may also be performed to minimize back side particle-related problems that occur during post-deposition processing such as photolithography.

Abstract: The embodiments provide apparatus and methods for removal of etch byproducts, dielectric films and metal films near the substrate bevel edge, and chamber interior to avoid the accumulation of polymer byproduct and deposited films and to improve process yield. In an exemplary embodiment, a plasma processing chamber configured to clean a bevel edge of a substrate is provided. The plasma processing chamber includes a substrate support configured to receive the substrate. The plasma processing chamber also includes a bottom edge electrode surrounding the substrate support. The bottom edge electrode and the substrate support are electrically isolated from one another by a bottom dielectric ring. A surface of the bottom edge electrode facing the substrate is covered by a bottom thin dielectric layer. The plasma processing chamber further includes a top edge electrode surrounding a top insulator plate opposing the substrate support. The top edge electrode is electrically grounded.

Abstract: A device for cleaning a bevel edge of a semiconductor substrate. The device includes: a lower support having a cylindrical top portion; a lower plasma-exclusion-zone (PEZ) ring surrounding the outer edge of the top portion and adapted to support the substrate; an upper dielectric component opposing the lower support and having a cylindrical bottom portion; an upper PEZ ring surrounding the outer edge of the bottom portion and opposing the lower PEZ ring; and at least one radiofrequency (RF) power source operative to energize process gas into plasma in an annular space defined by the upper and lower PEZ rings, wherein the annular space encloses the bevel edge.