Patents by Inventor Yunsheng Song

Yunsheng Song has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10109046
    Abstract: Systems for and methods of detecting faults in semiconductor wafers are provided. One method includes, for instance: monitoring, with at least one sensor, a recipe for manufacturing a semiconductor wafer; tracking, with a fault detection system, a set of steps for the recipe; determining a start of a step; sensing a set of data related to at least one parameter of the step; generating, by an imaging system, an image of the set of data; displaying, on a display, the image of the set of data; calculating, by the fault detection system, a pixel area ratio from the image of the set of data; determining if a fault exists in the wafer based upon the pixel area ratio; and displaying, on the display, an indication of the fault during real-time and at an end of the step.
    Type: Grant
    Filed: July 19, 2016
    Date of Patent: October 23, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Robert Boyd Finlay, Yunsheng Song
  • Publication number: 20180025483
    Abstract: Systems for and methods of detecting faults in semiconductor wafers are provided. One method includes, for instance: monitoring, with at least one sensor, a recipe for manufacturing a semiconductor wafer; tracking, with a fault detection system, a set of steps for the recipe; determining a start of a step; sensing a set of data related to at least one parameter of the step; generating, by an imaging system, an image of the set of data; displaying, on a display, the image of the set of data; calculating, by the fault detection system, a pixel area ratio from the image of the set of data; determining if a fault exists in the wafer based upon the pixel area ratio; and displaying, on the display, an indication of the fault during real-time and at an end of the step.
    Type: Application
    Filed: July 19, 2016
    Publication date: January 25, 2018
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Robert Boyd FINLAY, Yunsheng SONG
  • Patent number: 9780007
    Abstract: A test structure for an integrated circuit device includes a series inductor, capacitor, resistor (LCR) circuit having one or more inductor elements, with each inductor element having at least one unit comprising a first segment formed in a first metal layer, a second segment connecting the first metal layer to a semiconductor substrate beneath the first metal layer, and a third segment formed in the semiconductor substrate; and a capacitor element connected in series with each inductor element, the capacitor element defined by a transistor gate structure including a gate electrode as a first electrode, a gate dielectric layer, and the semiconductor substrate as a second electrode.
    Type: Grant
    Filed: January 4, 2012
    Date of Patent: October 3, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Xu Ouyang, Yunsheng Song, Tso-Hui Ting, Yongchun Xin
  • Patent number: 9559051
    Abstract: A method for depositing a conductor in the via opening electronic structure removes the via bottom liner so that the conductor deposited in the via opening directly contacts the underlying conductive layer. The method includes depositing amorphous silicon over the dielectric layer and the liner layer on the via opening sidewalls and bottom. The amorphous silicon extends substantially over the entire via opening while leaving below a void within the via opening. The amorphous silicon over the via opening and on the via opening bottom and the liner layer on the via opening bottom are anisotropically etched to leave a layer of amorphous silicon over the dielectric layer and the via opening side walls. The amorphous silicon is then removed to form a via opening having a substantially open-bottom liner. The conductor is then deposited in the via opening and contacts the underlying conductive layer.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: January 31, 2017
    Assignee: GlobalFoundries Inc.
    Inventors: Yongchun Xin, Jang H. Sim, Junjing Bao, Zhigang Song, Yunsheng Song
  • Patent number: 9524930
    Abstract: A modularized interposer includes a plurality of interposer units that are assembled to provide a complete set of electrical connections between two semiconductor chips. At least some of the plurality of interposer units can be replaced with other interposer units having an alternate configuration to enable selection of different functional parts of semiconductor chips to be connected through the modularized interposer. Bonding structures, connected to conductive metal pads located at peripheries of neighboring interposer units and an overlying or underlying portion of a semiconductor chip, can provide electrical connections between the neighboring interposer units. The interposer units can be provided by forming through-substrate vias (TSV's) in a substrate, forming patterned conductive structures on the substrate, and cutting the substrate into interposers.
    Type: Grant
    Filed: January 29, 2014
    Date of Patent: December 20, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Oleg Gluschenkov, Yunsheng Song, Tso-Hui Ting, Ping-Chuan Wang
  • Patent number: 9519210
    Abstract: A method for designing, a structure, method of inspecting and a computer system for designing voltage contrast integrated circuit characterization. The design method includes selecting a design level of a mask design shapes file; selecting a region of the design level having an open region having no design shapes and an adjacent circuit region having circuit design shapes; selecting a sub-region of the circuit region adjacent to the open region; copying design shapes of the sub-region to generate a characterization cell identical to the sub-region; modifying the characterization cell to generate a passive voltage contrast characterization cell; and placing the passive voltage contrast characterization cell into the open region adjacent to the sub-region to generate a modified design level.
    Type: Grant
    Filed: November 21, 2014
    Date of Patent: December 13, 2016
    Assignee: International Business Machines Corporation
    Inventors: Oliver D. Patterson, Yunsheng Song, Zhigang Song, Yongchun Xin
  • Publication number: 20160148849
    Abstract: A method for designing, a structure, method of inspecting and a computer system for designing voltage contrast integrated circuit characterization. The design method includes selecting a design level of a mask design shapes file; selecting a region of the design level having an open region having no design shapes and an adjacent circuit region having circuit design shapes; selecting a sub-region of the circuit region adjacent to the open region; copying design shapes of the sub-region to generate a characterization cell identical to the sub-region; modifying the characterization cell to generate a passive voltage contrast characterization cell; and placing the passive voltage contrast characterization cell into the open region adjacent to the sub-region to generate a modified design level.
    Type: Application
    Filed: November 21, 2014
    Publication date: May 26, 2016
    Inventors: Oliver D. Patterson, Yunsheng Song, Zhigang Song, Yongchun Xin
  • Patent number: 9337334
    Abstract: A semiconductor memory device including a channel region and a ferromagnetic gate is provided. The channel region can be formed within a semiconductor nanowire. The ferromagnetic gate is programmed with a selected orientation of magnetization by the electrical current that passes through the channel region in one direction or another. The orientation of the magnetization in the ferromagnetic gate can be detected by changes in the threshold voltage of a field effect transistor employing the ferromagnetic gate as a gate electrode, or can be detected by the resistance of the channel region that changes with the orientation of the magnetization in a two terminal device.
    Type: Grant
    Filed: April 21, 2014
    Date of Patent: May 10, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hari V. Mallela, Edward J. Nowak, Yunsheng Song, Reinaldo A. Vega, Keith Kwong Hon Wong, Zhijian Yang
  • Publication number: 20150303313
    Abstract: A semiconductor memory device including a channel region and a ferromagnetic gate is provided. The channel region can be formed within a semiconductor nanowire. The ferromagnetic gate is programmed with a selected orientation of magnetization by the electrical current that passes through the channel region in one direction or another. The orientation of the magnetization in the ferromagnetic gate can be detected by changes in the threshold voltage of a field effect transistor employing the ferromagnetic gate as a gate electrode, or can be detected by the resistance of the channel region that changes with the orientation of the magnetization in a two terminal device.
    Type: Application
    Filed: April 21, 2014
    Publication date: October 22, 2015
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hari V. Mallela, Edward J. Nowak, Yunsheng Song, Reinaldo A. Vega, Keith Kwong Hon Wong, Zhijian Yang
  • Patent number: 9151781
    Abstract: A set of first substrate and second substrate are manufactured with a built-in N-fold rotational symmetry around the center axis of each substrate, wherein N is an integer greater than 1. A set of N different interposers is provided such that an i-th interposer provides electrical connection between the first substrate and the second substrate with a rotational angle of (i?1)/NĂ—2?. The first and second substrates are tested with each of the N different interposers therebetween. Once the rotational angle that provides the highest stacked chip yield is determined, the first and the second substrates can be bonded with an azimuthal rotation that provides the highest stacked chip yield.
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: October 6, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Oleg Gluschenkov, Muthukumarasamy Karthikeyan, Yunsheng Song, Tso-Hui Ting, Richard P. Volant, Ping-Chuan Wang
  • Patent number: 9029234
    Abstract: One of the wafers in a semiconductor wafer to wafer stack can be rotated a predefined number of positions, relative to a previous wafer in the stack, and bonded in the position in which the maximum number of good die are aligned. An adjustment circuit on each die reroutes signals received from a pad that has been relocated due to rotation. A communication channel formed from a pair of pads that are interconnected by a Through Substrate Vias can be placed in each die and can convey selected information from one die to the next. A code representative of the position orientation of each die can be recorded in a Programmable Read Only Memory located on each die, or may be down loaded from a remote source. Any additional wafer may be stacked serially, and each one may be rotated relative to the wafer that precedes it in the stack.
    Type: Grant
    Filed: May 15, 2012
    Date of Patent: May 12, 2015
    Assignee: International Business Machines Corporation
    Inventors: John Matthew Safran, Daniel Jacob Fainstein, Gary W. Maier, Yunsheng Song, Norman Whitelaw Robson
  • Patent number: 8803328
    Abstract: Randomized coded arrays and method of forming a randomized coded array. The methods include: forming a dielectric layer on a semiconductor substrate; forming an array of openings extending through the dielectric layer; introducing particles into a random set of less than all of the openings; and forming a conductive material in each opening of the array of openings, thereby creating the randomized coded array, wherein a first resistance of a pathway through the conductive material in openings containing the particles is different from a second resistance of a path through openings not containing the particles. Also, a physically unclonable function embodied in a circuit.
    Type: Grant
    Filed: January 22, 2013
    Date of Patent: August 12, 2014
    Assignee: International Business Machines Corporation
    Inventors: Yunsheng Song, Keith Kwong Hon Wong, Yongchun Xin, Zhijian Yang
  • Publication number: 20140203448
    Abstract: Randomized coded arrays and methods of forming a randomized coded array. The methods include: forming a dielectric layer on a semiconductor substrate; forming an array of openings extending through the dielectric layer; introducing particles into a random set of less than all of the openings; and forming a conductive material in each opening of the array of openings, thereby creating the randomized coded array, wherein a first resistance of a pathway through the conductive material in openings containing the particles is different from a second resistance of a path through openings not containing the particles. Also, a physically unclonable function embodied in a circuit.
    Type: Application
    Filed: January 22, 2013
    Publication date: July 24, 2014
    Applicant: International Business Machines Corporation
    Inventors: Yunsheng Song, Keith Kwong Hon Wong, Yongchun Xin, Zhijian Yang
  • Patent number: 8759152
    Abstract: A modularized interposer includes a plurality of interposer units that are assembled to provide a complete set of electrical connections between two semiconductor chips. At least some of the plurality of interposer units can be replaced with other interposer units having an alternate configuration to enable selection of different functional parts of semiconductor chips to be connected through the modularized interposer. Bonding structures, connected to conductive metal pads located at peripheries of neighboring interposer units and an overlying or underlying portion of a semiconductor chip, can provide electrical connections between the neighboring interposer units. The interposer units can be provided by forming through-substrate vias (TSV's) in a substrate, forming patterned conductive structures on the substrate, and cutting the substrate into interposers.
    Type: Grant
    Filed: June 6, 2012
    Date of Patent: June 24, 2014
    Assignee: International Business Machines Corporation
    Inventors: Oleg Gluschenkov, Yunsheng Song, Tso-Hui Ting, Ping-Chuan Wang
  • Publication number: 20140145351
    Abstract: A modularized interposer includes a plurality of interposer units that are assembled to provide a complete set of electrical connections between two semiconductor chips. At least some of the plurality of interposer units can be replaced with other interposer units having an alternate configuration to enable selection of different functional parts of semiconductor chips to be connected through the modularized interposer. Bonding structures, connected to conductive metal pads located at peripheries of neighboring interposer units and an overlying or underlying portion of a semiconductor chip, can provide electrical connections between the neighboring interposer units. The interposer units can be provided by forming through-substrate vias (TSV's) in a substrate, forming patterned conductive structures on the substrate, and cutting the substrate into interposers.
    Type: Application
    Filed: January 29, 2014
    Publication date: May 29, 2014
    Applicant: International Business Machines Corporation
    Inventors: Oleg Gluschenkov, Yunsheng Song, Tso-Hui Ting, Ping-Chuan Wang
  • Publication number: 20130307159
    Abstract: One of the wafers in a semiconductor wafer to wafer stack can be rotated a predefined number of positions, relative to a previous wafer in the stack, and bonded in the position in which the maximum number of good die are aligned. An adjustment circuit on each die reroutes signals received from a pad that has been relocated due to rotation. A communication channel formed from a pair of pads that are interconnected by a Through Substrate Vias can be placed in each die and can convey selected information from one die to the next. A code representative of the position orientation of each die can be recorded in a Programmable Read Only Memory located on each die, or may be down loaded from a remote source. Any additional wafer may be stacked serially, and each one may be rotated relative to the wafer that precedes it in the stack.
    Type: Application
    Filed: May 15, 2012
    Publication date: November 21, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John Matthew Safran, Daniel Jacob Fainstein, Gary W. Maier, Yunsheng Song, Norman Whitelaw Robson
  • Patent number: 8489225
    Abstract: A system for performing alignment of two wafers is disclosed. The system comprises an optical coherence tomography system and a wafer alignment system. The wafer alignment system is configured and disposed to control the relative position of a first wafer and a second wafer. The optical coherence tomography system is configured and disposed to compute coordinate data for a plurality of alignment marks on the first wafer and second wafer, and send that coordinate data to the wafer alignment system.
    Type: Grant
    Filed: March 8, 2011
    Date of Patent: July 16, 2013
    Assignee: International Business Machines Corporation
    Inventors: Yongchun Xin, Xu Ouyang, Yunsheng Song, Tso-Hui Ting
  • Publication number: 20130169308
    Abstract: A test structure for an integrated circuit device includes a series inductor, capacitor, resistor (LCR) circuit having one or more inductor elements, with each inductor element having at least one unit comprising a first segment formed in a first metal layer, a second segment connecting the first metal layer to a semiconductor substrate beneath the first metal layer, and a third segment formed in the semiconductor substrate; and a capacitor element connected in series with each inductor element, the capacitor element defined by a transistor gate structure including a gate electrode as a first electrode, a gate dielectric layer, and the semiconductor substrate as a second electrode.
    Type: Application
    Filed: January 4, 2012
    Publication date: July 4, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Xu Ouyang, Yunsheng Song, Tso-Hui Ting, Yongchun Xin
  • Patent number: 8429193
    Abstract: A system and a method are provided. The method includes assigning an entity to a ticket group associated with an ID thereof, displaying to the entity reports, which are each organized with an associated security access control, in accordance with the ticket group, determining whether the entity is authorized to access any selected one or more of the reports in accordance with a result of a comparison between an access level associated with the entity ID and the security access control associated with each of the one or more of the stored reports, and granting or denying the access in accordance with the determination.
    Type: Grant
    Filed: January 9, 2009
    Date of Patent: April 23, 2013
    Assignee: International Business Machines Corporation
    Inventors: Yunsheng Song, Tso-Hui Ting, Brian M. Trapp
  • Patent number: 8369976
    Abstract: A method for increasing overall yield in semiconductor manufacturing including routing wafers or wafer lots from tool to tool in a manner which at least partially neutralizes or compensates for processing variations. A system for increasing overall yield in semiconductor manufacturing includes a module for recording processing data from plural first and second types of tools and a module for routing wafers or wafer lots from tools of the first type of tools to tools of the second type of tools so as to at least partially neutralizes or compensate for processing variation.
    Type: Grant
    Filed: June 23, 2008
    Date of Patent: February 5, 2013
    Assignee: International Business Machines Corporation
    Inventors: Keith Kwong Hon Wong, Xu Ouyang, Yunsheng Song