Abstract: An array substrate is provided. The array substrate includes a plurality of first reset signal lines configured to provide a plurality of first reset signals, a plurality of second reset signal lines configured to provide a plurality of second reset signals, a plurality of third reset signal lines, and a plurality of first connecting lines. A respective first reset signal line is connected to a row of first connecting lines, which in turn are connected to source electrodes of first reset transistors in a row of subpixels, respectively. The plurality of second reset signal lines and the plurality of third reset signal lines form an interconnected reset signal supply network. A respective second reset signal line is connected to one or more of the plurality of third reset signal lines. A respective third reset signal line is connected to one or more of the plurality of second reset signal lines.

Abstract: A display substrate and a display apparatus are disclosed. The display substrate includes: a base substrate including a first and second display regions; a light transmittance of the first display region is greater than that of the second display region; first sub-pixels in the first display region. At least one first sub-pixel includes a first pixel circuit and a first light emitting device; the first pixel circuit includes a storage capacitor and a driving transistor; and a data writing sub-circuit configured to write a data voltage signal to a gate electrode of the driving transistor in response to a first and second scan signals; a reset sub-circuit configured to provide an initialization voltage signal to a first electrode of the first light emitting device in response to the second scan signal; and a luminescent control sub-circuit configured to transmit a driving current to the first light emitting device.

Abstract: Systems for and methods of detecting faults in semiconductor wafers are provided. One method includes, for instance: monitoring, with at least one sensor, a recipe for manufacturing a semiconductor wafer; tracking, with a fault detection system, a set of steps for the recipe; determining a start of a step; sensing a set of data related to at least one parameter of the step; generating, by an imaging system, an image of the set of data; displaying, on a display, the image of the set of data; calculating, by the fault detection system, a pixel area ratio from the image of the set of data; determining if a fault exists in the wafer based upon the pixel area ratio; and displaying, on the display, an indication of the fault during real-time and at an end of the step.

Abstract: Systems for and methods of detecting faults in semiconductor wafers are provided. One method includes, for instance: monitoring, with at least one sensor, a recipe for manufacturing a semiconductor wafer; tracking, with a fault detection system, a set of steps for the recipe; determining a start of a step; sensing a set of data related to at least one parameter of the step; generating, by an imaging system, an image of the set of data; displaying, on a display, the image of the set of data; calculating, by the fault detection system, a pixel area ratio from the image of the set of data; determining if a fault exists in the wafer based upon the pixel area ratio; and displaying, on the display, an indication of the fault during real-time and at an end of the step.

Abstract: A test structure for an integrated circuit device includes a series inductor, capacitor, resistor (LCR) circuit having one or more inductor elements, with each inductor element having at least one unit comprising a first segment formed in a first metal layer, a second segment connecting the first metal layer to a semiconductor substrate beneath the first metal layer, and a third segment formed in the semiconductor substrate; and a capacitor element connected in series with each inductor element, the capacitor element defined by a transistor gate structure including a gate electrode as a first electrode, a gate dielectric layer, and the semiconductor substrate as a second electrode.

Abstract: A method for depositing a conductor in the via opening electronic structure removes the via bottom liner so that the conductor deposited in the via opening directly contacts the underlying conductive layer. The method includes depositing amorphous silicon over the dielectric layer and the liner layer on the via opening sidewalls and bottom. The amorphous silicon extends substantially over the entire via opening while leaving below a void within the via opening. The amorphous silicon over the via opening and on the via opening bottom and the liner layer on the via opening bottom are anisotropically etched to leave a layer of amorphous silicon over the dielectric layer and the via opening side walls. The amorphous silicon is then removed to form a via opening having a substantially open-bottom liner. The conductor is then deposited in the via opening and contacts the underlying conductive layer.

Abstract: A modularized interposer includes a plurality of interposer units that are assembled to provide a complete set of electrical connections between two semiconductor chips. At least some of the plurality of interposer units can be replaced with other interposer units having an alternate configuration to enable selection of different functional parts of semiconductor chips to be connected through the modularized interposer. Bonding structures, connected to conductive metal pads located at peripheries of neighboring interposer units and an overlying or underlying portion of a semiconductor chip, can provide electrical connections between the neighboring interposer units. The interposer units can be provided by forming through-substrate vias (TSV's) in a substrate, forming patterned conductive structures on the substrate, and cutting the substrate into interposers.

Abstract: A method for designing, a structure, method of inspecting and a computer system for designing voltage contrast integrated circuit characterization. The design method includes selecting a design level of a mask design shapes file; selecting a region of the design level having an open region having no design shapes and an adjacent circuit region having circuit design shapes; selecting a sub-region of the circuit region adjacent to the open region; copying design shapes of the sub-region to generate a characterization cell identical to the sub-region; modifying the characterization cell to generate a passive voltage contrast characterization cell; and placing the passive voltage contrast characterization cell into the open region adjacent to the sub-region to generate a modified design level.

Abstract: A method for designing, a structure, method of inspecting and a computer system for designing voltage contrast integrated circuit characterization. The design method includes selecting a design level of a mask design shapes file; selecting a region of the design level having an open region having no design shapes and an adjacent circuit region having circuit design shapes; selecting a sub-region of the circuit region adjacent to the open region; copying design shapes of the sub-region to generate a characterization cell identical to the sub-region; modifying the characterization cell to generate a passive voltage contrast characterization cell; and placing the passive voltage contrast characterization cell into the open region adjacent to the sub-region to generate a modified design level.

Abstract: A semiconductor memory device including a channel region and a ferromagnetic gate is provided. The channel region can be formed within a semiconductor nanowire. The ferromagnetic gate is programmed with a selected orientation of magnetization by the electrical current that passes through the channel region in one direction or another. The orientation of the magnetization in the ferromagnetic gate can be detected by changes in the threshold voltage of a field effect transistor employing the ferromagnetic gate as a gate electrode, or can be detected by the resistance of the channel region that changes with the orientation of the magnetization in a two terminal device.

Abstract: A semiconductor memory device including a channel region and a ferromagnetic gate is provided. The channel region can be formed within a semiconductor nanowire. The ferromagnetic gate is programmed with a selected orientation of magnetization by the electrical current that passes through the channel region in one direction or another. The orientation of the magnetization in the ferromagnetic gate can be detected by changes in the threshold voltage of a field effect transistor employing the ferromagnetic gate as a gate electrode, or can be detected by the resistance of the channel region that changes with the orientation of the magnetization in a two terminal device.

Abstract: A set of first substrate and second substrate are manufactured with a built-in N-fold rotational symmetry around the center axis of each substrate, wherein N is an integer greater than 1. A set of N different interposers is provided such that an i-th interposer provides electrical connection between the first substrate and the second substrate with a rotational angle of (i?1)/N×2?. The first and second substrates are tested with each of the N different interposers therebetween. Once the rotational angle that provides the highest stacked chip yield is determined, the first and the second substrates can be bonded with an azimuthal rotation that provides the highest stacked chip yield.

Abstract: One of the wafers in a semiconductor wafer to wafer stack can be rotated a predefined number of positions, relative to a previous wafer in the stack, and bonded in the position in which the maximum number of good die are aligned. An adjustment circuit on each die reroutes signals received from a pad that has been relocated due to rotation. A communication channel formed from a pair of pads that are interconnected by a Through Substrate Vias can be placed in each die and can convey selected information from one die to the next. A code representative of the position orientation of each die can be recorded in a Programmable Read Only Memory located on each die, or may be down loaded from a remote source. Any additional wafer may be stacked serially, and each one may be rotated relative to the wafer that precedes it in the stack.

Abstract: Randomized coded arrays and method of forming a randomized coded array. The methods include: forming a dielectric layer on a semiconductor substrate; forming an array of openings extending through the dielectric layer; introducing particles into a random set of less than all of the openings; and forming a conductive material in each opening of the array of openings, thereby creating the randomized coded array, wherein a first resistance of a pathway through the conductive material in openings containing the particles is different from a second resistance of a path through openings not containing the particles. Also, a physically unclonable function embodied in a circuit.

Abstract: Randomized coded arrays and methods of forming a randomized coded array. The methods include: forming a dielectric layer on a semiconductor substrate; forming an array of openings extending through the dielectric layer; introducing particles into a random set of less than all of the openings; and forming a conductive material in each opening of the array of openings, thereby creating the randomized coded array, wherein a first resistance of a pathway through the conductive material in openings containing the particles is different from a second resistance of a path through openings not containing the particles. Also, a physically unclonable function embodied in a circuit.

Abstract: A modularized interposer includes a plurality of interposer units that are assembled to provide a complete set of electrical connections between two semiconductor chips. At least some of the plurality of interposer units can be replaced with other interposer units having an alternate configuration to enable selection of different functional parts of semiconductor chips to be connected through the modularized interposer. Bonding structures, connected to conductive metal pads located at peripheries of neighboring interposer units and an overlying or underlying portion of a semiconductor chip, can provide electrical connections between the neighboring interposer units. The interposer units can be provided by forming through-substrate vias (TSV's) in a substrate, forming patterned conductive structures on the substrate, and cutting the substrate into interposers.

Abstract: A modularized interposer includes a plurality of interposer units that are assembled to provide a complete set of electrical connections between two semiconductor chips. At least some of the plurality of interposer units can be replaced with other interposer units having an alternate configuration to enable selection of different functional parts of semiconductor chips to be connected through the modularized interposer. Bonding structures, connected to conductive metal pads located at peripheries of neighboring interposer units and an overlying or underlying portion of a semiconductor chip, can provide electrical connections between the neighboring interposer units. The interposer units can be provided by forming through-substrate vias (TSV's) in a substrate, forming patterned conductive structures on the substrate, and cutting the substrate into interposers.

Abstract: One of the wafers in a semiconductor wafer to wafer stack can be rotated a predefined number of positions, relative to a previous wafer in the stack, and bonded in the position in which the maximum number of good die are aligned. An adjustment circuit on each die reroutes signals received from a pad that has been relocated due to rotation. A communication channel formed from a pair of pads that are interconnected by a Through Substrate Vias can be placed in each die and can convey selected information from one die to the next. A code representative of the position orientation of each die can be recorded in a Programmable Read Only Memory located on each die, or may be down loaded from a remote source. Any additional wafer may be stacked serially, and each one may be rotated relative to the wafer that precedes it in the stack.

Abstract: A system for performing alignment of two wafers is disclosed. The system comprises an optical coherence tomography system and a wafer alignment system. The wafer alignment system is configured and disposed to control the relative position of a first wafer and a second wafer. The optical coherence tomography system is configured and disposed to compute coordinate data for a plurality of alignment marks on the first wafer and second wafer, and send that coordinate data to the wafer alignment system.

Abstract: A test structure for an integrated circuit device includes a series inductor, capacitor, resistor (LCR) circuit having one or more inductor elements, with each inductor element having at least one unit comprising a first segment formed in a first metal layer, a second segment connecting the first metal layer to a semiconductor substrate beneath the first metal layer, and a third segment formed in the semiconductor substrate; and a capacitor element connected in series with each inductor element, the capacitor element defined by a transistor gate structure including a gate electrode as a first electrode, a gate dielectric layer, and the semiconductor substrate as a second electrode.