Abstract: A system and method for fail pattern analysis for a memory device is disclosed. The peripheral circuits of a memory device are divided into different zones based on circuit design and layout. Defects are detected by inline inspection of multiple SRAM devices at various stages in the manufacturing process and saved into a database. When the devices are fabricated, electrical tests are then performed. Electrical failure patterns are also recorded and saved in the database. A correlation between the zone in which a visual defect resides and an electrical failure is recorded in computer storage. Visual defects found during inline inspection are then associated with an electrical failure in the memory device.

Abstract: Monitoring a process sector in a production facility includes establishing a tool defect index associated with a process sector in the production facility. The tool defect index includes a signal representing a defect factor associated with a tool in the process sector. Monitoring the process also requires determining whether the defect factor is a known defect factor or an unknown defect factor, and analyzing a unit from the tool if the defect factor is an unknown defect factor. Monitoring the process further requires identifying at least one defect on the unit from the tool, establishing that the at least one defect is a significant defect, determining cause of the significant defect, and creating an alert indicating that the tool associated with the process sector is producing units having significant defects.

Abstract: A method of detecting low-probability defects in large transistor arrays (such as large arrays of SRAM cells), where the defects manifest themselves as asymmetrical leakage in a transistor (such as a pulldown nFET in an SRAM cell). These defects are detected by creating one or more test arrays, identical in all regards to the large transistor arrays up until the contact and metallization layers. Leakage is measured by applying an appropriate off-state voltage (e.g., 0V) by a common connection to all of the gates of the transistors in the test array, then measuring the aggregate drain/source leakage current, both forward and reverse (e.g., first grounded source and positively biased drain, then grounded drain and positively biased source) comparing the difference between the two leakage current measurements.

Abstract: A modularized interposer includes a plurality of interposer units that are assembled to provide a complete set of electrical connections between two semiconductor chips. At least some of the plurality of interposer units can be replaced with other interposer units having an alternate configuration to enable selection of different functional parts of semiconductor chips to be connected through the modularized interposer. Bonding structures, connected to conductive metal pads located at peripheries of neighboring interposer units and an overlying or underlying portion of a semiconductor chip, can provide electrical connections between the neighboring interposer units. The interposer units can be provided by forming through-substrate vias (TSV's) in a substrate, forming patterned conductive structures on the substrate, and cutting the substrate into interposers.

Abstract: A system for performing alignment of two wafers is disclosed. The system comprises an optical coherence tomography system and a wafer alignment system. The wafer alignment system is configured and disposed to control the relative position of a first wafer and a second wafer.

Abstract: A modularized interposer includes a plurality of interposer units that are assembled to provide a complete set of electrical connections between two semiconductor chips. At least some of the plurality of interposer units can be replaced with other interposer units having an alternate configuration to enable selection of different functional parts of semiconductor chips to be connected through the modularized interposer. Bonding structures, connected to conductive metal pads located at peripheries of neighboring interposer units and an overlying or underlying portion of a semiconductor chip, can provide electrical connections between the neighboring interposer units. The interposer units can be provided by forming through-substrate vias (TSV's) in a substrate, forming patterned conductive structures on the substrate, and cutting the substrate into interposers.

Abstract: A method of analyzing production steps includes inputting application data associated with a production process having a plurality of process steps into a memory with each of the plurality of process steps including a plurality of tools. The method also includes loading process data associated with one of the plurality of process steps into the memory, performing a tool commonality analysis on each of the tools associated with the at least one of the plurality of process steps, identifying all tool-to-tool differences for the at least one of the plurality of process steps, performing a tool stratification analysis to identify one of the plurality of tools that provides the largest variance contribution to the at least one of the plurality of process steps, and stopping the one of the plurality of tools that provides the largest variance contribution to the at least one of the plurality of process steps.

Abstract: A set of first substrate and second substrate are manufactured with a built-in N-fold rotational symmetry around the center axis of each substrate, wherein N is an integer greater than 1. A set of N different interposers is provided such that an i-th interposer provides electrical connection between the first substrate and the second substrate with a rotational angle of (i?1)/N×2?. The first and second substrates are tested with each of the N different interposers therebetween. Once the rotational angle that provides the highest stacked chip yield is determined, the first and the second substrates can be bonded with an azimuthal rotation that provides the highest stacked chip yield.

Abstract: A set of first substrate and second substrate are manufactured with a built-in N-fold rotational symmetry around the center axis of each substrate, wherein N is an integer greater than 1. A set of N different interposers is provided such that an i-th interposer provides electrical connection between the first substrate and the second substrate with a rotational angle of (i?1)/N×2?. The first and second substrates are tested with each of the N different interposers therebetween. Once the rotational angle that provides the highest stacked chip yield is determined, the first and the second substrates can be bonded with an azimuthal rotation that provides the highest stacked chip yield.

Abstract: A method of failure detection of an integrated circuit (IC) layout includes determining a critical path distance between a first geometric feature of the IC layout and a second geometric feature of the IC layout; and comparing the determined critical path distance to a defined minimum critical path distance between the first and second geometric features, wherein the defined minimum critical path distance corresponds to a desired electrical property of the IC layout, independent of any geometric-based ground rule minimum distance for the IC layout; identifying any determined critical path distances that are less than the defined minimum critical path distance as a design violation; and modifying the IC layout by eliminating the identified design violations.

Abstract: A method for increasing overall yield in semiconductor manufacturing including routing wafers or wafer lots based on process variation data obtained from the wafers or wafer lots and on process variation data obtained from tools processing the wafers or wafer lots. A system for increasing overall yield in semiconductor manufacturing includes a module for routing wafers or wafer lots based on process variation data obtained from the wafers or wafer lots and on process variation data obtained from the tools processing the wafers or wafer lots.

Abstract: Methods, systems, and computer program products for implementing product randomization and analysis in a manufacturing environment are provided. A method includes processing products for a plurality of lots, at process equipment, using a randomization technique for selecting each product in the lots. The method further including generating an operation identification record for each operation in the process recipe that includes mapping, for each operation, a slot identifier associated with a randomly selected product to a process variable identifier, a process tool, and the operation. The method also includes defining slot groupings using slot identifiers for a product carrier and identifying product yield patterns by analyzing historical yields for each of the slot groupings.

Abstract: A method of optimizing production cycle queue time includes selecting a plurality of process steps for a production cycle, calculating queue times for each of the plurality of process steps, statistically analyzing the queue times, and generating at least one visual output that illustrates the statistically analyzed queue times.

Abstract: A method for optimizing multiple process windows in a semiconductor manufacturing process is disclosed. The method comprises performing dependent variable composition on a plurality of dependent variables. Metrology data is joined with the dependent variables, and then a partial least squares regression is performed on the joined data set to obtain a prediction equation, and a variable importance prediction for each process window in a process window set. A set of product limited yield are derived, and the process window, set is adjusted, and the yields recalculated, until an optimal process window set is derived.

Abstract: Excluding variations attributable to equipment from split analysis is performed by identifying dependent variables related to at least one of the split analysis or an experiment to be performed. A test is performed to ascertain whether or not a variation attributable to equipment exists with respect to any of the identified dependent variables. If such a variation exists, a target data set and a training data set are constructed. A signature is identified for the variation. A statistical model is selected based upon the identified signature. The selected statistical model is constructed using the training data set to generate a statistical output. The target data set is joined with the statistical output. The identified dependent variables in the target data set are adjusted using the statistical output. The target data set including the adjusted identified dependent variables is loaded to an application for performing split analysis.

Abstract: A modularized interposer includes a plurality of interposer units that are assembled to provide a complete set of electrical connections between two semiconductor chips. At least some of the plurality of interposer units can be replaced with other interposer units having an alternate configuration to enable selection of different functional parts of semiconductor chips to be connected through the modularized interposer. Bonding structures, connected to conductive metal pads located at peripheries of neighboring interposer units and an overlying or underlying portion of a semiconductor chip, can provide electrical connections between the neighboring interposer units. The interposer units can be provided by forming through-substrate vias (TSV's) in a substrate, forming patterned conductive structures on the substrate, and cutting the substrate into interposers.

Abstract: A method of failure detection of an integrated circuit (IC) layout includes determining a critical path distance between a first geometric feature of the IC layout and a second geometric feature of the IC layout; and comparing the determined critical path distance to a defined minimum critical path distance between the first and second geometric features, wherein the defined minimum critical path distance corresponds to a desired electrical property of the IC layout, independent of any geometric-based ground rule minimum distance for the IC layout; identifying any determined critical path distances that are less than the defined minimum critical path distance as a design violation; and modifying the IC layout by eliminating the identified design violations.

Abstract: A set of first substrate and second substrate are manufactured with a built-in N-fold rotational symmetry around the center axis of each substrate, wherein N is an integer greater than 1. A set of N different interposers is provided such that an i-th interposer provides electrical connection between the first substrate and the second substrate with a rotational angle of (i?1)/N×2?. The first and second substrates are tested with each of the N different interposers therebetween. Once the rotational angle that provides the highest stacked chip yield is determined, the first and the second substrates can be bonded with an azimuthal rotation that provides the highest stacked chip yield.

Abstract: A method of analyzing production steps includes inputting application data associated with a production process having a plurality of process steps into a memory with each of the plurality of process steps including a plurality of tools. The method also includes loading process data associated with one of the plurality of process steps into the memory, performing a tool commonality analysis on each of the tools associated with the at least one of the plurality of process steps, identifying all tool-to-tool differences for the at least one of the plurality of process steps, performing a tool stratification analysis to identify one of the plurality of tools that provides the largest variance contribution to the at least one of the plurality of process steps, and stopping the one of the plurality of tools that provides the largest variance contribution to the at least one of the plurality of process steps.

Abstract: A method of establishing a lot grading system for lots in a semiconductor manufacturing process includes defining a new lot grade for at least one lot in the semiconductor manufacturing process. The at least one lot is has a current lot grade and the new lot grade is dependent upon the current lot grade. The new lot grade is saved in a grading referenced database and the at least one lot in the semiconductor manufacturing process is updated with the new lot grade.