Patents by Inventor Yunteng Huang

Yunteng Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200254230
    Abstract: a dilatable balloon catheter, comprising: a guide wire inserted and disposed in the inside of the catheter, an operation portion is fixedly connected to one end of the catheter, a balloon is disposed at the outer side of the catheter remote from the operation portion, the lumen of the catheter and the inner cavity of the balloon are connected by a communication structure provided on the catheter, the guide wire includes a first guide wire and a second guide wire which are separated from each other, the rear end of the first guide wire is connected to insertion-extraction structure in the rear end of the operation portion, the second guide wire is fixed to the inside of the catheter by a fixing process.
    Type: Application
    Filed: October 17, 2017
    Publication date: August 13, 2020
    Applicant: INNOVEX MEDICAL CO., LTD.
    Inventors: Chang SHENG, Yunteng HUANG, Zhongwei ZHENG, Wei QIAN, Hang YAN
  • Publication number: 20200147352
    Abstract: A non-vascular lumen guide wire, comprising a mandrel (1) and a ball head (2) prepared with a metal material, wherein an outer diameter of the insertion end of the mandrel (1) is smaller than the outer diameter of the non-insertion end of the mandrel; the insertion end of the mandrel (1) is connected to the ball head (2), a plastic coating layer (3) is wrapped around the outer side of the mandrel (1), the outer diameter of the ball head (2) is larger than the outer diameter of the insertion end of the plastic coating layer (3), and the outer diameter of the ball head (2) is not larger than the non-insertion end of the plastic coating layer (3). The guide wire, by means of using a ball head (2) with a diameter slightly larger than the plastic coating layer (3) at a far end, may effectively avoid the defects that the guide wire falls off in actual use, or the plastic coating layer (3) at the far end easily rolls up when inserted.
    Type: Application
    Filed: October 25, 2017
    Publication date: May 14, 2020
    Applicant: INNOVEX MEDICAL CO., LTD.
    Inventors: Zhongwei Zheng, Yunteng HUANG, Qing YUAN, Pan WANG, Hang YAN
  • Publication number: 20190297395
    Abstract: A meter reader unit includes an image sensor that captures images of a face of a meter to produce image data. A computer vision processor recognizes meter data within the images. The meter data includes numerical values that indicate unit usages as measured by the meter. A wireless transceiver transmits the meter data to a remote entity. A power source provides power to the meter reader unit. A volume of the meter data transmitted to the remote entity is less than a volume of the image data so that power required to transmit the meter data is less than would be required to transmit the image data.
    Type: Application
    Filed: March 24, 2018
    Publication date: September 26, 2019
    Inventor: Yunteng Huang
  • Patent number: 10320509
    Abstract: Techniques for generating a fail safe clock signal improves reliability of one or more output clock signals generated based on one or more input clock signals and an internally generated reference clock signal. By continuously monitoring the frequencies of the one or more input clock signals and reducing or eliminating effects of any static frequency offset between multiple input clock signals, the fail safe clock generator can detect very small relative frequency changes between the inputs or within a particular input. By comparing the input clock frequencies against a reference clock signal frequency over time of a clock signal generated by an internal oscillator, the fail safe clock generator may further detect which one of multiple input clocks has frequency deviation. The fail safe clock generator uses an internal oscillator generating a reference clock signal having a short-term stable frequency.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: June 11, 2019
    Assignee: Silicon Laboratories Inc.
    Inventors: Yunteng Huang, Adam B. Eldredge, Gregory J. Richmond
  • Patent number: 10057051
    Abstract: A more cost effective wander jitter filter utilizes an excursion detector that receives a timing difference between a first signal and a second signal and supplies a first adjustment amount if a magnitude of the timing difference is above a predetermined threshold and otherwise supplies a second adjustment amount of zero. A summing circuit adjusts a magnitude of the timing difference by the first or second adjustment amount. A loop filter receives the summing circuit output and controls an oscillator. The excursion detector output (first adjustment value or zero according to the magnitude of the timing difference) is low pass filtered and the low pass filtered is reintroduced into the oscillator output or the feedback loop. The excursion detector output is accumulated and used to adjust a phase of the feedback signal from the oscillator.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: August 21, 2018
    Assignee: Silicon Laboratories Inc.
    Inventor: Yunteng Huang
  • Patent number: 9705668
    Abstract: A gap detector detects when a phase difference between a feedback signal and a clock signal is larger than a gap threshold. If the phase difference is larger than the gap threshold, then the phase difference is modified by subtracting a gap value from the phase difference. If the phase difference is less than the threshold, the phase difference is not modified. A loop filter receives and filters the modified or unmodified phase difference and controls an oscillator. An accumulator circuit accumulates the modified phase difference and supplies a phase adjust signal. A low pass filter receives the phase adjust signal and supplies a filtered phase adjust signal that is used to slowly adjust the output of the oscillator.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: July 11, 2017
    Assignee: Silicon Laboratories Inc.
    Inventor: Yunteng Huang
  • Publication number: 20170187481
    Abstract: Techniques for generating a fail safe clock signal improves reliability of one or more output clock signals generated based on one or more input clock signals and an internally generated reference clock signal. By continuously monitoring the frequencies of the one or more input clock signals and reducing or eliminating effects of any static frequency offset between multiple input clock signals, the fail safe clock generator can detect very small relative frequency changes between the inputs or within a particular input. By comparing the input clock frequencies against a reference clock signal frequency over time of a clock signal generated by an internal oscillator, the fail safe clock generator may further detect which one of multiple input clocks has frequency deviation. The fail safe clock generator uses an internal oscillator generating a reference clock signal having a short-term stable frequency.
    Type: Application
    Filed: December 28, 2015
    Publication date: June 29, 2017
    Inventors: Yunteng Huang, Adam B. Eldredge, Gregory J. Richmond
  • Patent number: 9621170
    Abstract: A micro electro mechanical system (MEMS) oscillator supplies an oscillator output signal having a first frequency that differs from a predetermined frequency of the output signal. An error determination circuit determines frequency error from the predetermined frequency based on initial frequency offset and/or temperature and provides the error information indicating a difference between the first frequency and the predetermined frequency. The error information is used by a receiving system in frequency translation logic that utilizes the oscillator output signal as a frequency reference.
    Type: Grant
    Filed: August 13, 2013
    Date of Patent: April 11, 2017
    Assignee: Silicon Laboratories Inc.
    Inventor: Yunteng Huang
  • Publication number: 20160352505
    Abstract: A gap detector detects when a phase difference between a feedback signal and a clock signal is larger than a gap threshold. If the phase difference is larger than the gap threshold, then the phase difference is modified by subtracting a gap value from the phase difference. If the phase difference is less than the threshold, the phase difference is not modified. A loop filter receives and filters the modified or unmodified phase difference and controls an oscillator. An accumulator circuit accumulates the modified phase difference and supplies a phase adjust signal. A low pass filter receives the phase adjust signal and supplies a filtered phase adjust signal that is used to slowly adjust the output of the oscillator.
    Type: Application
    Filed: May 29, 2015
    Publication date: December 1, 2016
    Inventor: Yunteng Huang
  • Publication number: 20160352506
    Abstract: A more cost effective wander jitter filter utilizes an excursion detector that receives a timing difference between a first signal and a second signal and supplies a first adjustment amount if a magnitude of the timing difference is above a predetermined threshold and otherwise supplies a second adjustment amount of zero. A summing circuit adjusts a magnitude of the timing difference by the first or second adjustment amount. A loop filter receives the summing circuit output and controls an oscillator. The excursion detector output (first adjustment value or zero according to the magnitude of the timing difference) is low pass filtered and the low pass filtered is reintroduced into the oscillator output or the feedback loop. The excursion detector output is accumulated and used to adjust a phase of the feedback signal from the oscillator.
    Type: Application
    Filed: December 30, 2015
    Publication date: December 1, 2016
    Inventor: Yunteng Huang
  • Publication number: 20160264299
    Abstract: A beverage container comprises a label. The label includes sections that are designed to be selectively removed. A plurality of indicia associated with the sections identify the removed sections.
    Type: Application
    Filed: March 12, 2015
    Publication date: September 15, 2016
    Inventors: Xiangdong Zhang, Yunteng Huang
  • Patent number: 9118392
    Abstract: A first integrated circuit die receives input data from a plurality of input channels and combines the input data from the plurality of input channels into combined data. The first integrated circuit die transmits the combined data across an isolation communication channel. A second integrated circuit die that is coupled to the isolation communication channel decodes the transmitted combined data and supplies the decoded transmitted combined data to respective output channels corresponding to the input channels.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: August 25, 2015
    Assignee: Silicon Laboratories Inc.
    Inventors: Siddharth Sundar, Michael J. Mills, Hua Zhu, Riad Wahby, Jeffrey L. Sonntag, Yunteng Huang, Anantha Nag Nemmani
  • Publication number: 20150048895
    Abstract: A micro electro mechanical system (MEMS) oscillator supplies an oscillator output signal having a first frequency that differs from a predetermined frequency of the output signal. An error determination circuit determines frequency error from the predetermined frequency based on initial frequency offset and/or temperature and provides the error information indicating a difference between the first frequency and the predetermined frequency. The error information is used by a receiving system in frequency translation logic that utilizes the oscillator output signal as a frequency reference.
    Type: Application
    Filed: August 13, 2013
    Publication date: February 19, 2015
    Applicant: Silicon Laboratories Inc.
    Inventor: Yunteng Huang
  • Publication number: 20140307759
    Abstract: A first integrated circuit die receives input data from a plurality of input channels and combines the input data from the plurality of input channels into combined data. The first integrated circuit die transmits the combined data across an isolation communication channel. A second integrated circuit die that is coupled to the isolation communication channel decodes the transmitted combined data and supplies the decoded transmitted combined data to respective output channels corresponding to the input channels.
    Type: Application
    Filed: September 30, 2013
    Publication date: October 16, 2014
    Applicant: Silicon Laboratories Inc.
    Inventors: Siddharth Sundar, Michael J. Mills, Hua Zhu, Riad Wahby, Jeffrey L. Sonntag, Yunteng Huang, Anantha Nag Nemmani
  • Patent number: 8860514
    Abstract: A fractional-N divider supplies a divided clock signal. An adjusted divided clock signal is generated in a digital-to-time converter circuit having a delay linearly proportional to digital quantization errors of the fractional-N divider. The adjusted divided clock signal is generated based on first and second capacitors charging to a predetermined level. The charging of the first and second capacitors is interleaved in alternate periods of the divided clock. The charging of each capacitor with a current corresponding to respective digital quantization errors is interleaved with charging with a fixed current. A first edge of a first pulse of the adjusted divided clock signal is generated in response to the first capacitor charging to a predetermined voltage and a first edge of a next pulse of the adjusted divided clock signal is generated in response to the second capacitor charging to the predetermined voltage.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: October 14, 2014
    Assignee: Silicon Laboratories Inc.
    Inventors: Colin Weltin-Wu, Yunteng Huang, Manu Seth
  • Patent number: 8786341
    Abstract: A digital frequency synthesizer provides absolute phase lock and shorter settling time through the use of a digital filter with a phase and frequency path. Control logic control disables the frequency path during the frequency acquisition and sets a wide bandwidth. After frequency acquisition, a counter with digital phase information is reset using the input clock signal to bring the output phase closer to lock with the input signal and the control logic enables the phase path in the digital loop filter to achieve phase lock with a narrower bandwidth than the initial bandwidth.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: July 22, 2014
    Assignee: Silicon Laboratories Inc.
    Inventors: Colin Weltin-Wu, Yunteng Huang
  • Publication number: 20140176201
    Abstract: A fractional-N divider supplies a divided clock signal. An adjusted divided clock signal is generated in a digital-to-time converter circuit having a delay linearly proportional to digital quantization errors of the fractional-N divider. The adjusted divided clock signal is generated based on first and second capacitors charging to a predetermined level. The charging of the first and second capacitors is interleaved in alternate periods of the divided clock. The charging of each capacitor with a current corresponding to respective digital quantization errors is interleaved with charging with a fixed current. A first edge of a first pulse of the adjusted divided clock signal is generated in response to the first capacitor charging to a predetermined voltage and a first edge of a next pulse of the adjusted divided clock signal is generated in response to the second capacitor charging to the predetermined voltage.
    Type: Application
    Filed: December 21, 2012
    Publication date: June 26, 2014
    Applicant: SILICON LABORATORIES INC.
    Inventors: Colin Weltin-Wu, Yunteng Huang, Manu Seth
  • Patent number: 8712344
    Abstract: A transmitter is adapted to be programmed to select an amplifier operating class for the transmitter out of a plurality of amplifier operating classes. The transmitter is also adapted to operate according to the selected amplifier operating class to communicate a signal to an antenna.
    Type: Grant
    Filed: March 31, 2011
    Date of Patent: April 29, 2014
    Assignee: Silicon Laboratories Inc.
    Inventors: Zhondga Wang, Sai Chu Wong, Yunteng Huang
  • Patent number: 8531246
    Abstract: A clock synthesis circuit includes a delta sigma modulator that receives a divide ratio and generates an integer portion and a digital quantization error (a fractional portion). A fractional-N divider divides a received signal according to a divide control value corresponding to the integer portion and generates a divided signal. A phase interpolator adjusts a phase of the divided signal according to the digital quantization error to thereby reduce noise associated with the fractional-N divider.
    Type: Grant
    Filed: November 16, 2010
    Date of Patent: September 10, 2013
    Assignee: Silicon Laboratories Inc.
    Inventor: Yunteng Huang
  • Patent number: 8471629
    Abstract: A power control circuit is coupled to receive a feedback signal from a power amplifier (PA) and generate a control signal to control a variable gain amplifier (VGA) coupled to an input to the PA based on the feedback signal. The power control circuit may include, in one embodiment, a mute circuit to generate a mute signal to be provided to the VGA when the control signal is less than a first level and a clamp circuit to clamp a control voltage used to generate the control signal from exceeding a threshold level.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: June 25, 2013
    Assignee: Silicon Laboratories Inc
    Inventors: Axel Thomsen, Zhongda Wang, Sai Chu Wong, Yunteng Huang