Patents by Inventor Yuri Mirgorodski

Yuri Mirgorodski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8669157
    Abstract: The number of times that a non-volatile memory (NVM) can be programmed and erased is substantially increased by utilizing a localized heating element that anneals the oxide that is damaged by tunneling charge carriers when the NVM is programmed and erased. The program and erase voltages are also reduced when heat from the heating element is applied prior to programming and erasing.
    Type: Grant
    Filed: May 21, 2012
    Date of Patent: March 11, 2014
    Assignee: National Semiconductor Corporation
    Inventors: Jeffrey A. Babcock, Yuri Mirgorodski, Natalia Lavrovskaya, Saurabh Desai
  • Patent number: 8554529
    Abstract: A method of simulating an integrated circuit device under test (DUT) is provided, wherein the DUT includes a plurality of terminals. For each terminal of the DUT, a probe pulse is applied to the terminal and a reaction is recorded at the terminal and each of the other terminals to obtain values representative of reactive tails for the terminal. For each terminal, the values representative of the reactive tails obtained for the terminal are stored as an entry of a look-up table. Each entry includes n+x fields, wherein n represents a number of arguments in the entry and x represents a number of functions in the entry. For each terminal, a signal value at a selected time step is calculated.
    Type: Grant
    Filed: November 30, 2007
    Date of Patent: October 8, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Yuri Mirgorodski, Peter J. Hopper, William French, Philipp Lindorfer
  • Patent number: 8453494
    Abstract: A semiconductor-based gas detector enhances the collection of gas molecules and also provides a self-contained means for removing collected gas molecules by utilizing one or more electric fields to transport the gas molecules to and away from a metallic material that has a high permeability to the gas molecules.
    Type: Grant
    Filed: September 13, 2010
    Date of Patent: June 4, 2013
    Assignee: National Semiconductor Corporation
    Inventors: Jeffrey A. Babcock, Peter J. Hopper, Yuri Mirgorodski
  • Publication number: 20120230118
    Abstract: The number of times that a non-volatile memory (NVM) can be programmed and erased is substantially increased by utilizing a localized heating element that anneals the oxide that is damaged by tunneling charge carriers when the NVM is programmed and erased. The program and erase voltages are also reduced when heat from the heating element is applied prior to programming and erasing.
    Type: Application
    Filed: May 21, 2012
    Publication date: September 13, 2012
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jeffrey A. Babcock, Yuri Mirgorodski, Natalia Lavrovskaya, Saurabh Desai
  • Patent number: 8247862
    Abstract: A method is provided for enhancing charge storage in an E2PROM cell structure that includes a read transistor having spaced apart source an drain diffusion regions formed in a semiconductor substrate to define a substrate channel region therebetween, a conductive charge storage element formed over the substrate channel region and separated therefrom by gate dielectric material, a conductive control gate that is separated from the charge storage element by intervening dielectric material, and a conductive heating element disposed in proximity to the charge storage element. The method comprises performing a programming operation that causes charge to be placed on the charge storage element and, during the programming operation, heating the heating element to a temperature such that heat is provided to the charge storage element.
    Type: Grant
    Filed: March 2, 2010
    Date of Patent: August 21, 2012
    Assignee: National Semiconductor Corporation
    Inventors: Jeff A Babcock, Yuri Mirgorodski, Natalia Lavrovskaya, Saurabh Desai
  • Patent number: 8207578
    Abstract: A method for forming a doped region of a semiconductor device includes masking a portion of a substrate with a mask. The mask is configured to create a graded doping profile within the doped region. The method also includes performing an implant using the mask to create doped areas and undoped areas in the substrate. The method further includes diffusing the doped areas to create the graded doping profile in the doped region. The mask could include a first region having openings distributed throughout a photo-resist material, where the openings vary in size and spacing. The mask could also include a second region having blocks of photo-resist material distributed throughout an open region, where the photo-resist blocks vary in size and spacing. Diffusing the doped areas could include applying a high temperature anneal to smooth the doped and undoped areas to produce a linearly graded doping profile.
    Type: Grant
    Filed: June 8, 2011
    Date of Patent: June 26, 2012
    Assignee: National Semiconductor Corporation
    Inventors: William French, Erika Mazotti, Yuri Mirgorodski
  • Patent number: 8183621
    Abstract: The number of times that a non-volatile memory (NVM) can be programmed and erased is substantially increased by utilizing a localized heating element that anneals the oxide that is damaged by tunneling charge carriers when the NVM is programmed and erased. The program and erase voltages are also reduced when heat from the heating element is applied prior to programming and erasing.
    Type: Grant
    Filed: February 28, 2011
    Date of Patent: May 22, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Jeffrey A. Babcock, Yuri Mirgorodski, Natalia Lavrovskaya, Saurabh Desai
  • Publication number: 20120060587
    Abstract: A semiconductor-based gas detector enhances the collection of gas molecules and also provides a self-contained means for removing collected gas molecules by utilizing one or more electric fields to transport the gas molecules to and away from a metallic material that has a high permeability to the gas molecules.
    Type: Application
    Filed: September 13, 2010
    Publication date: March 15, 2012
    Inventors: Jeffrey A. Babcock, Peter J. Hopper, Yuri Mirgorodski
  • Publication number: 20110233670
    Abstract: A method for forming a doped region of a semiconductor device includes masking a portion of a substrate with a mask. The mask is configured to create a graded doping profile within the doped region. The method also includes performing an implant using the mask to create doped areas and undoped areas in the substrate. The method further includes diffusing the doped areas to create the graded doping profile in the doped region. The mask could include a first region having openings distributed throughout a photo-resist material, where the openings vary in size and spacing. The mask could also include a second region having blocks of photo-resist material distributed throughout an open region, where the photo-resist blocks vary in size and spacing. Diffusing the doped areas could include applying a high temperature anneal to smooth the doped and undoped areas to produce a linearly graded doping profile.
    Type: Application
    Filed: June 8, 2011
    Publication date: September 29, 2011
    Applicant: National Semiconductor Corporation
    Inventors: William French, Erika Mazotti, Yuri Mirgorodski
  • Patent number: 7978519
    Abstract: A method of reading an NVM cell structure formed on a deep well of N-type semiconductor material, wherein the NVM cell structure includes a PMOS transistor formed in an N-type well, the PMOS transistor including spaced-apart p-type source and drain region defining an n-type cannel region therebetween, an NMOS transistor formed in a P-type well that is adjacent to the N-type well, the NMOS transistor including spaced-apart n-type source and drain regions defining a p-type channel region therebetween, a conductive floating gate that includes a first section that extends over the n-type channel region of the PMOS transistor and is separated therefrom by intervening dielectric material and a second section that extends over the p-type channel region and is separated therefrom by intervening dielectric material, and a conductive control gate formed over at least a portion of the second section of the floating gate and is separated therefrom by intervening dielectric material, the method comprising: biasing the dee
    Type: Grant
    Filed: September 17, 2010
    Date of Patent: July 12, 2011
    Assignee: National Semiconductor Corporation
    Inventors: Yuri Mirgorodski, Peter J. Hopper, Roozbeh Parsa
  • Patent number: 7969790
    Abstract: A method of erasing an NVM cell structure formed on a deep well of N-type semiconductor material, wherein the NVM cell structure includes a PMOS transistor formed in an N-type well, the PMOS transistor including spaced-apart p-type source and drain regions defining an n-type channel region therebetween, an NMOS transistor formed in a P-type well that is adjacent to the N-type well, the NMOS transistor including spaced-apart n-type source and rain regions defining a p-type channel region therebetween, a conductive floating gate that includes a first section that extends over the n-type channel region of the PMOS transistor and is separated therefrom by intervening dielectric material and a second section that extends over the p-type channel region and is separated therefrom by intervening dielectric material, and a conductive control gate formed over at least a portion of the second section of the floating gate and separated therefrom by intervening dielectric material, the erasing method comprising: biasing t
    Type: Grant
    Filed: September 17, 2010
    Date of Patent: June 28, 2011
    Assignee: National Semiconductor Corporation
    Inventors: Yuri Mirgorodski, Peter J. Hopper, Roozbeh Parsa
  • Publication number: 20110147820
    Abstract: The number of times that a non-volatile memory (NVM) can be programmed and erased is substantially increased by utilizing a localized heating element that anneals the oxide that is damaged by tunneling charge carriers when the NVM is programmed and erased. The program and erase voltages are also reduced when heat from the heating element is applied prior to programming and erasing.
    Type: Application
    Filed: February 28, 2011
    Publication date: June 23, 2011
    Inventors: Jeffrey A. Babcock, Yuri Mirgorodski, Natalia Lavrovskaya, Saurabh Desai
  • Patent number: 7964485
    Abstract: A method for forming a doped region of a semiconductor device includes masking a portion of a substrate with a mask. The mask is configured to create a graded doping profile within the doped region. The method also includes performing an implant using the mask to create doped areas and undoped areas in the substrate. The method further includes diffusing the doped areas to create the graded doping profile in the doped region. The mask could include a first region having openings distributed throughout a photo-resist material, where the openings vary in size and spacing. The mask could also include a second region having blocks of photo-resist material distributed throughout an open region, where the photo-resist blocks vary in size and spacing. Diffusing the doped areas could include applying a high temperature anneal to smooth the doped and undoped areas to produce a linearly graded doping profile.
    Type: Grant
    Filed: October 23, 2009
    Date of Patent: June 21, 2011
    Assignee: National Semiconductor Corporation
    Inventors: William French, Erika Mazotti, Yuri Mirgorodski
  • Patent number: 7919805
    Abstract: In a non-volatile memory cell, a single poly SOI technology is used to save space and achieve low current programming by providing two capacitors formed in an n-material over an NBL, forming a inverter in an n-material over a PBL, and isolating the NBL from the PBL by means of a lightly doped region or a deep trench isolation region.
    Type: Grant
    Filed: May 25, 2007
    Date of Patent: April 5, 2011
    Assignee: National Semiconductor Corporation
    Inventors: Yuri Mirgorodski, Natalia Lavrovskaya, Saurabh Desai
  • Patent number: 7919807
    Abstract: The number of times that a non-volatile memory (NVM) can be programmed and erased is substantially increased by utilizing a localized heating element that anneals the oxide that is damaged by tunneling charge carriers when the NVM is programmed and erased. The program and erase voltages are also reduced when heat from the heating element is applied prior to programming and erasing.
    Type: Grant
    Filed: March 29, 2007
    Date of Patent: April 5, 2011
    Assignee: National Semiconductor Corporation
    Inventors: Jeffrey A. Babcock, Yuri Mirgorodski, Natalia Lavrovskaya, Saurabh Desai
  • Patent number: 7911869
    Abstract: In a programmable circuit making use of fuse cells, a snapback NMOS or NPN transistor or SCR without reversible snapback capability is used as an anti-fuse, and programming comprises biasing the control electrode of the transistor to cause the transistor to go into snapback mode.
    Type: Grant
    Filed: August 5, 2005
    Date of Patent: March 22, 2011
    Assignee: National Semiconductor Corporation
    Inventors: Vladislav Vashchenko, Peter J. Hopper, Yuri Mirgorodski
  • Publication number: 20110007570
    Abstract: A method of reading an NVM cell structure formed on a deep well of N-type semiconductor material, wherein the NVM cell structure includes a PMOS transistor formed in an N-type well, the PMOS transistor including spaced-apart p-type source and drain region defining an n-type cannel region therebetween, an NMOS transistor formed in a P-type well that is adjacent to the N-type well, the NMOS transistor including spaced-apart n-type source and drain regions defining a p-type channel region therebetween, a conductive floating gate that includes a first section that extends over the n-type channel region of the PMOS transistor and is separated therefrom by intervening dielectric material and a second section that extends over the p-type channel region and is separated therefrom by intervening dielectric material, and a conductive control gate formed over at least a portion of the second section of the floating gate and is separated therefrom by intervening dielectric material, the method comprising: biasing the dee
    Type: Application
    Filed: September 17, 2010
    Publication date: January 13, 2011
    Applicant: NATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Yuri Mirgorodski, Peter J. Hopper, Roozbeh Parsa
  • Publication number: 20110007574
    Abstract: A method of erasing an NVM cell structure formed on a deep well of N-type semiconductor material, wherein the NVM cell structure includes a PMOS transistor formed in an N-type well, the PMOS transistor including spaced-apart p-type source and drain regions defining an n-type channel region therebetween, an NMOS transistor formed in a P-type well that is adjacent to the N-type well, the NMOS transistor including spaced-apart n-type source and rain regions defining a p-type channel region therebetween, a conductive floating gate that includes a first section that extends over the n-type channel region of the PMOS transistor and is separated therefrom by intervening dielectric material and a second section that extends over the p-type channel region and is separated therefrom by intervening dielectric material, and a conductive control gate formed over at least a portion of the second section of the floating gate and separated therefrom by intervening dielectric material, the erasing method comprising: biasing t
    Type: Application
    Filed: September 17, 2010
    Publication date: January 13, 2011
    Applicant: NATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Yuri Mirgorodski, Peter J. Hopper, Roozbeh Parsa
  • Patent number: 7859912
    Abstract: A method of operating a non-volatile memory (NVM) cell structure that utilizes gated diode is provided. The cell architecture, utilizing about 4-10 um2 per bit, includes gated diodes that are used to program the cells while consuming low programming current. The cell architecture also allows a large number of cells to be programmed at the same time, thereby reducing the effective programming time per bit. Erase and read mode bias conditions are also provided.
    Type: Grant
    Filed: August 12, 2009
    Date of Patent: December 28, 2010
    Assignee: National Semiconductor Corporation
    Inventors: Yuri Mirgorodski, Peter J. Hopper, Roozbeh Parsa
  • Patent number: 7808034
    Abstract: In a non-volatile memory cell, charge is stored in a fully isolated substrate or floating bulk that forms a storage capacitor with a first poly strip and includes a second poly strip defining a control gate and a third poly strip coupled to a read transistor gate.
    Type: Grant
    Filed: January 12, 2007
    Date of Patent: October 5, 2010
    Assignee: National Semiconductor Corporation
    Inventors: Jeff Babcock, Natasha Layrovskava, Yuri Mirgorodski, Saurahh Desai