Patents by Inventor Yuri Mirgorodski
Yuri Mirgorodski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20100157682Abstract: A method is provided for enhancing charge storage in an E2PROM cell structure that includes a read transistor having spaced apart source an drain diffusion regions formed in a semiconductor substrate to define a substrate channel region therebetween, a conductive charge storage element formed over the substrate channel region and separated therefrom by gate dielectric material, a conductive control gate that is separated from the charge storage element by intervening dielectric material, and a conductive heating element disposed in proximity to the charge storage element. The method comprises performing a programming operation that causes charge to be placed on the charge storage element and, during the programming operation, heating the heating element to a temperature such that heat is provided to the charge storage element.Type: ApplicationFiled: March 2, 2010Publication date: June 24, 2010Applicant: National Semiconductor CorporationInventors: Jeff A. Babcock, Yuri Mirgorodski, Natalia Lavrovskaya, Saurabh Desai
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Patent number: 7719048Abstract: A heating element is utilized to improve the bias conditions of an E2PROM cell during program and erase operations. The heating element can also be used to anneal or condition the cell for improved charge storage. During a program or an erase operation, the cell's control gate and read transistor are set to ground. The heating element then has a voltage potential applied across its terminals, causing current to flow in this resistor. As the current density increases, the resistor begins to generate heat. This heat is thermally coupled into the cell's floating gate, causing its temperature to rise.Type: GrantFiled: April 26, 2007Date of Patent: May 18, 2010Assignee: National Semiconductor CorporationInventors: Jeff A. Babcock, Yuri Mirgorodski, Natalia Lavrovskaya, Saurabh Desai
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Patent number: 7705403Abstract: In a LVTSCR or snapback NMOS ESD structure, low voltage protection as well as higher voltage protection is provided by introducing a floating gate that capacitively couples with the control gate of the ESD structure and programming the floating gate to have different charges on it as desired.Type: GrantFiled: January 3, 2006Date of Patent: April 27, 2010Assignee: National Semiconductor CorporationInventors: Vladislav Vashchenko, Yuri Mirgorodski, Peter J. Hopper
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Patent number: 7663173Abstract: In a non-volatile memory cell, charge is stored in a fully isolated substrate or floating bulk that forms a storage capacitor with a first poly strip and includes a second poly strip defining a read gate and a poly-filled trench defining a control gate.Type: GrantFiled: January 12, 2007Date of Patent: February 16, 2010Assignee: National Semiconductor CorporationInventors: Saurabh Desai, Natasha Lavrovskaya, Yuri Mirgorodski, Jeff Babcock
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Patent number: 7651913Abstract: An electrical shield is provided in a non-volatile memory (NVM) cell structure to protect the cell's floating gate from any influence resulting from charge redistribution in the vicinity of the floating gate during a programming operation. The shield may be created from the second polysilicon layer or other conductive material covering the floating gate. The shield may be grounded. Alternately, it may be connected to the cell's control gate electrode resulting in better coupling between the floating gate and the control gate. It is not necessary that the shield cover the floating gate completely, the necessary protective effect is achieved if the coupling to the dielectric layers surrounding the floating gate is reduced.Type: GrantFiled: February 4, 2008Date of Patent: January 26, 2010Assignee: National Semiconductor CorporationInventors: Yuri Mirgorodski, Peter J. Hopper, Vladislav Vashchenko
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Patent number: 7651897Abstract: A method for manufacturing a chip with a metal heat flow path extending between a terminal of a transistor thereof and bulk semiconductor material of the chip (e.g., from the terminal to a substrate over which the transistor is formed or to the body of a semiconductor device adjacent to the transistor). The chip can be implemented by a semiconductor on insulator (SOI) process and can include at least one bipolar or MOS transistor, an insulator underlying the transistor, a semiconductor substrate underlying the insulator, and a metal heat flow path extending between a terminal of the transistor through the insulator to the substrate. Preferably, the metal heat flow path is a metal interconnect formed by a process step (or steps) of the same type performed to produce other metal interconnects of the chip.Type: GrantFiled: October 10, 2007Date of Patent: January 26, 2010Assignee: National Semiconductor CorporationInventors: Vladislav Vashchenko, Peter J. Hopper, Yuri Mirgorodski
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Publication number: 20090296493Abstract: A method of operating a non-volatile memory (NVM) cell structure that utilizes gated diode is provided. The cell architecture, utilizing about 4-10 um2 per bit, includes gated diodes that are used to program the cells while consuming low programming current. The cell architecture also allows a large number of cells to be programmed at the same time, thereby reducing the effective programming time per bit. Erase and read mode bias conditions are also provided.Type: ApplicationFiled: August 12, 2009Publication date: December 3, 2009Applicant: NATIONAL SEMICONDUCTOR CORPORATIONInventors: Yuri Mirgorodski, Peter J. Hopper, Roozbeh Parsa
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Publication number: 20090144035Abstract: A modified “black box” integrated circuit simulation model is provided that is based only upon on the external steady-state and transient characteristics of a device under test (DUT). The method utilizes probe pulses as well as steady-state I-V and C-V look-up tables. In contrast to conventional black box simulation models, which support only steady-state and small signal frequency analysis, the disclosed method also supports large signal transient analysis.Type: ApplicationFiled: November 30, 2007Publication date: June 4, 2009Inventors: Yuri Mirgorodski, Peter J. Hopper, William French, Philipp Lindorfer
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Patent number: 7435628Abstract: A vertical MOS transistor has a source region, a channel region, and a drain region that are vertically stacked, and a trench that extends from the top surface of the drain region through the drain region, the channel region, and partially into the source region. The vertical MOS transistor also has an insulation layer that lines the trench, and a conductive gate region that contacts the insulation layer to fill up the trench.Type: GrantFiled: July 27, 2007Date of Patent: October 14, 2008Assignee: National Semiconductor CorporationInventors: Peter J. Hopper, Yuri Mirgorodski, Vladislav Vashchenko, Peter Johnson
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Patent number: 7425741Abstract: A biased conductive plate is provided over an NVM cell structure to overcome data retention charge loss due to the presence of dielectric films that are conductive at higher temperatures. The biased conductive plate is preferably formed from the lowest metal layer in the fabrication process flow, but any biased conductive layer can be used.Type: GrantFiled: July 21, 2005Date of Patent: September 16, 2008Assignee: National Semiconductor CorporationInventors: Andrew Strachan, Natalia Lavrovskaya, Saurabh Desai, Roozbeh Parsa, Yuri Mirgorodski
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Patent number: 7422952Abstract: A ballasting region is placed between the base region and the collector contact of a bipolar junction transistor to relocate a hot spot away from the collector contact of the transistor. Relocating the hot spot away from the collector contact prevents the collector contact from melting during an electrostatic discharge (ESD) pulse.Type: GrantFiled: May 3, 2007Date of Patent: September 9, 2008Assignee: National Semiconductor CorporationInventors: Vladislav Vashchenko, Peter J. Hopper, Yuri Mirgorodski
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Publication number: 20080213959Abstract: An electrical shield is provided in a non-volatile memory (NVM) cell structure to protect the cell's floating gate from any influence resulting from charge redistribution in the vicinity of the floating gate during a programming operation. The shield may be created from the second polysilicon layer or other conductive material covering the floating gate. The shield may be grounded. Alternately, it may be connected to the cell's control gate electrode resulting in better coupling between the floating gate and the control gate. It is not necessary that the shield cover the floating gate completely, the necessary protective effect is achieved if the coupling to the dielectric layers surrounding the floating gate is reduced.Type: ApplicationFiled: February 4, 2008Publication date: September 4, 2008Inventors: Yuri Mirgorodski, Peter J. Hopper, Vladislav Vashchenko
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Patent number: 7375393Abstract: An electrical shield is provided in a non-volatile memory (NVM) cell structure to protect the cell's floating gate from any influence resulting from charge redistribution in the vicinity of the floating gate during a programming operation. The shield may be created from the second polysilicon layer or other conductive material covering the floating gate. The shield may be grounded. Alternately, it may be connected to the cell's control gate electrode resulting in better coupling between the floating gate and the control gate. It is not necessary that the shield cover the floating gate completely, the necessary protective effect is achieved if the coupling to the dielectric layers surrounding the floating gate is reduced.Type: GrantFiled: January 27, 2005Date of Patent: May 20, 2008Assignee: National Semiconductor CorporationInventors: Yuri Mirgorodski, Peter J. Hopper, Vladislav Vashchenko
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Patent number: 7339835Abstract: Feedback between the floating gate voltage and a high erase voltage is utilized in the erase operation of a non-volatile memory (NVM) cell. Erasing stops when the floating gate voltage reaches the threshold voltage of the controlling transistor, making the variability of the NVM cell's threshold voltage the same as a regular device in the integrated circuit structure, thereby reducing the significant threshold voltage variability in erased NVM cells.Type: GrantFiled: February 14, 2005Date of Patent: March 4, 2008Assignee: National Semiconductor CorporationInventors: Yuri Mirgorodski, Peter J. Hopper, Vladislav Vashchenko
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Publication number: 20080032467Abstract: In some embodiments, a chip with a metal heat flow path extending between a terminal of a transistor thereof and bulk semiconductor material of the chip (e.g., from the terminal to a substrate over which the transistor is formed or to the body of a semiconductor device adjacent to the transistor) and methods for manufacturing such a chip. The chip can be implemented by a semiconductor on insulator (SOI) process and can include at least one bipolar or MOS transistor, an insulator underlying the transistor, a semiconductor substrate underlying the insulator, and a metal heat flow path extending between a terminal of the transistor through the insulator to the substrate. Preferably, the metal heat flow path is a metal interconnect formed by a process step (or steps) of the same type performed to produce other metal interconnects of the chip.Type: ApplicationFiled: October 10, 2007Publication date: February 7, 2008Applicant: NATIONAL SEMICONDUCTOR CORPORATIONInventors: Vladislav Vashchenko, Peter Hopper, Yuri Mirgorodski
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Patent number: 7298599Abstract: A snapback ESD protection network coupled across first and second integrated circuit pads and including first and second snapback devices, such as SCR devices, with the second device having a turnoff current ITOFF which is greater than the turnoff current of the first device. Each of the snapback devices has an anode terminal and a cathode terminal, with the first device anode and cathode terminals being coupled to the respective first and second integrated circuit pads through a first effective series resistance and the second device being coupled to the respective first and second integrated circuit pads through a second effective series resistance, with the first effective series resistance being smaller than the second so as to cause the first and second snapback devices to tend to turn on at about the same time at the beginning of an ESD event. The differences in turnoff current cause the second snapback device to turn off prior to the first snapback device at the conclusion of an ESD event.Type: GrantFiled: August 13, 2004Date of Patent: November 20, 2007Assignee: National Semiconductor CorporationInventors: Vladislav Vashchenko, Peter J. Hopper, Yuri Mirgorodski, Philip Lindorpher
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Patent number: 7298653Abstract: In an EEPROM array the cells are pre-charged or pre-erased so that they will respond uniformly to the same read voltage level. By clearly defining the threshold voltage for the cells in their erased states and in their programmed states, it is possible to define more than one read voltage and thus provide cells that an store multiple values and even analog values.Type: GrantFiled: June 21, 2004Date of Patent: November 20, 2007Assignee: National Semiconductor CorporationInventors: Peter J. Hopper, Philipp Lindorfer, Vladislav Vashchenko, Yuri Mirgorodski
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Patent number: 7262401Abstract: An active pixel sensor cell including at least one photodiode and reset circuitry and an integrating varactor coupled to the photodiode, a method for reading out such a cell, and an image sensor including an array of such cells. The photodiode can be exposed to photons during an exposure interval to accumulate a sequence of subexposure charges at a first node of the photodiode. Each of the subexposure charges accumulates at the first node during a different subexposure interval of the exposure interval. The photodiode is reset during each of a sequence of reset intervals, each reset interval occurring before a different one of the subexposure intervals. An output signal indicative of an exposure charge accumulated at the storage node during the exposure interval can be asserted from the cell, where the exposure charge is indicative of a sum of all the subexposure charges.Type: GrantFiled: August 1, 2006Date of Patent: August 28, 2007Assignee: Eastman Kodak CompanyInventors: Peter J. Hopper, Philipp Lindorfer, Mark W. Poulter, Yuri Mirgorodski
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Patent number: 7259411Abstract: A vertical MOS transistor has a source region, a channel region, and a drain region that are vertically stacked, and a trench that extends from the top surface of the drain region through the drain region, the channel region, and partially into the source region. The vertical MOS transistor also has an insulation layer that lines the trench, and a conductive gate region that contacts the insulation layer to fill up the trench.Type: GrantFiled: December 4, 2003Date of Patent: August 21, 2007Assignee: National Semiconductor CorporationInventors: Peter J. Hopper, Yuri Mirgorodski, Vladislav Vashchenko, Peter Johnson
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Patent number: 7233521Abstract: A storage device that is capable of receiving an analog signal and storing it as a digital signal. The storage device includes an input node configured to receive an analog input voltage and two non-volatile storage cells. A second non-volatile memory cell is coupled to receive the analog input signal from the input node. The second non-volatile memory cell is capable of being programmed to a one of a plurality of programming states. The first non-volatile memory cell, which is coupled to the second non-volatile memory cell, is also capable of being programmed to one of a plurality of programming states. During operation, the second non-volatile memory cell and the first non-volatile memory cell are both programmed to a selected second programming state indicative of the magnitude of the analog input voltage. The first programming state and the second programming state are together are indicative of a digital value commensurate with the magnitude of the analog input voltage.Type: GrantFiled: March 11, 2005Date of Patent: June 19, 2007Assignee: National Semiconductor CorporationInventors: Yuri Mirgorodski, Peter J. Hopper, Vladislav Vashshenco, Philipp Lindorfer