Patents by Inventor Yuriy Pavlenko

Yuriy Pavlenko has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210048954
    Abstract: Command scheduling for die sets of non-volatile memory may be performed based on command states of the die sets. Upon receiving an erase command to erase data stored in a first block set of non-volatile memory, a command state of the first die set of the non-volatile memory is determined, where the first die set contains the first block set. If the first die set is determined to be in a pending command state, the erase command is queued in a wait queue. If the first die set is determined to be in an idle command state, the erase command is scheduled to erase the data stored in the first block set.
    Type: Application
    Filed: October 30, 2020
    Publication date: February 18, 2021
    Inventors: YungLi JI, Yun-Tzuo LAI, Haining LIU, Yuriy PAVLENKO
  • Patent number: 10872039
    Abstract: A controller selects a redundancy context for eviction in response to a request for a redundancy context. The redundancy context includes buffer data and an identifier. The redundancy context is evicted by instructing a redundancy component to send the buffer data and identifier to a memory component to store in a buffer as an evicted context. The controller instructs the memory component to provide the evicted context for storage in a controller buffer. A new redundancy context is allocated to the requester following the eviction.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: December 22, 2020
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: James P. Crowley, Yuriy Pavlenko, Karl D. Schuh
  • Patent number: 10846000
    Abstract: Command scheduling for die sets of non-volatile memory may be performed based on command states of the die sets. Upon receiving an erase command to erase data stored in a first block set of non-volatile memory, a command state of the first die set of the non-volatile memory is determined, where the first die set contains the first block set. If the first die set is determined to be in a pending command state, the erase command is queued in a wait queue. If the first die set is determined to be in an idle command state, the erase command is scheduled to erase the data stored in the first block set.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: November 24, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: YungLi Ji, Yun-Tzuo Lai, Haining Liu, Yuriy Pavlenko
  • Publication number: 20200218679
    Abstract: The subject technology provides for managing a data storage system. Commands are identified into as a first command type or a second command type. The commands identified as the first command type are assigned to a first queue, and the commands identified as the second command type are assigned to a second queue. After the commands from the first queue and the commands from the second queue are processed based on a scheduling ratio over a predetermined period of time, a write amplification factor, number of host read commands, and number of host write commands during the predetermined period of time are determined. The scheduling ratio is updated based on the write amplification, the number of host read commands, the number of host write commands, and a predetermined scheduling ratio factor. Subsequent commands are processed from the first queue and the second queue based on the updated scheduling ratio.
    Type: Application
    Filed: March 23, 2020
    Publication date: July 9, 2020
    Inventors: Scott JINN, Yun-Tzuo LAI, Haining LIU, Yuriy PAVLENKO
  • Publication number: 20200174935
    Abstract: A controller selects a redundancy context for eviction in response to a request for a redundancy context. The redundancy context includes buffer data and an identifier. The redundancy context is evicted by instructing a redundancy component to send the buffer data and identifier to a memory component to store in a buffer as an evicted context. The controller instructs the memory component to provide the evicted context for storage in a controller buffer. A new redundancy context is allocated to the requester following the eviction.
    Type: Application
    Filed: December 3, 2018
    Publication date: June 4, 2020
    Inventors: James P. Crowley, Yuriy Pavlenko, Karl D. Schuh
  • Publication number: 20200159418
    Abstract: A storage device may include a controller and a memory array including a plurality of dies arranged into a plurality of channels. In some examples, the controller may be configured to define, from the memory array, a plurality of die-sets based on respective chip enable lines associated with the plurality of dies, wherein each die-set of the plurality of die-sets includes at least one die from each of the plurality of channels; define, from a selected die-set of the plurality of die-sets, a plurality of blocksets, wherein each blockset includes a block from each die of the selected die-set; receive a unit of data to be stored; and issue commands that cause the unit of data to be stored in blocks of a selected blockset of the plurality of blocksets.
    Type: Application
    Filed: January 23, 2020
    Publication date: May 21, 2020
    Inventors: Haining LIU, Yuriy PAVLENKO, George G. ARTNAK, JR.
  • Patent number: 10635617
    Abstract: The subject technology provides for managing a data storage system. Commands are identified into as a first command type or a second command type. The commands identified as the first command type are assigned to a first queue, and the commands identified as the second command type are assigned to a second queue. After the commands from the first queue and the commands from the second queue are processed based on a scheduling ratio over a predetermined period of time, a write amplification factor, number of host read commands, and number of host write commands during the predetermined period of time are determined. The scheduling ratio is updated based on the write amplification, the number of host read commands, the number of host write commands, and a predetermined scheduling ratio factor. Subsequent commands are processed from the first queue and the second queue based on the updated scheduling ratio.
    Type: Grant
    Filed: May 19, 2017
    Date of Patent: April 28, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Scott Jinn, Yun-Tzuo Lai, Haining Liu, Yuriy Pavlenko
  • Patent number: 10552055
    Abstract: A storage device may include a controller and a memory array including a plurality of dies arranged into a plurality of channels. In some examples, the controller may be configured to define, from the memory array, a plurality of die-sets based on respective chip enable lines associated with the plurality of dies, wherein each die-set of the plurality of die-sets includes at least one die from each of the plurality of channels; define, from a selected die-set of the plurality of die-sets, a plurality of blocksets, wherein each blockset includes a block from each die of the selected die-set; receive a unit of data to be stored; and issue commands that cause the unit of data to be stored in blocks of a selected blockset of the plurality of blocksets.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: February 4, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Haining Liu, Yuriy Pavlenko, George G. Artnak, Jr.
  • Publication number: 20200026597
    Abstract: The subject technology provides for managing a data storage system. A data operation error for a data operation initiated in a first non-volatile memory die of a plurality of non-volatile memory die in the data storage system is detected. An error count for an error type of the data operation error for the first non-volatile memory die is incremented. The incremented error count satisfies a first threshold value for the error type of the data operation error is determined. The first non-volatile memory die is marked for exclusion from subsequent data operations.
    Type: Application
    Filed: September 27, 2019
    Publication date: January 23, 2020
    Inventors: Sanghoon CHU, Scott JINN, Yuriy PAVLENKO, Kum-Jung SONG
  • Publication number: 20200027520
    Abstract: The subject technology provides implementations, which may be included as part of firmware of the flash memory device, that will not solely rely on a flash controller interpreted status but includes additional checks to the returned flash status byte. Each flash read, write, and erase command requires a status read command to determine the state of operation. Depending on the particular command issued, each bit of the returned status has a different meaning. The flash memory device firmware can check whether an illogical or inconsistent status is present. For example, if an overall pass/fail bit indicates a “pass” but a plane pass/fail bit indicates a “fail” then there could be an erroneous detection. Also, for every operation, the firmware can read status twice when the flash memory is ready. If the second status byte fails to match the first status byte then a die may be flagged as failing.
    Type: Application
    Filed: September 27, 2019
    Publication date: January 23, 2020
    Inventors: Sanghoon CHU, Scott JINN, Yuriy PAVLENKO
  • Publication number: 20190347174
    Abstract: A device that provides power fail handling using command suspension includes non-volatile memory circuits and a controller that is configured to determine that a power fail event has occurred. The controller is configured to determine, in response to the determination that the power fail event has occurred, which of the non-volatile memory circuits are executing a first type of memory commands. The controller is also configured to issue a stop command to the determined non-volatile memory circuits to stop execution of the first type of memory commands.
    Type: Application
    Filed: July 26, 2019
    Publication date: November 14, 2019
    Inventors: YungLi JI, Yuriy PAVLENKO, Kum-Jung SONG
  • Patent number: 10452468
    Abstract: The subject technology provides for managing a data storage system. A data operation error for a data operation initiated in a first non-volatile memory die of a plurality of non-volatile memory die in the data storage system is detected. An error count for an error type of the data operation error for the first non-volatile memory die is incremented. The incremented error count satisfies a first threshold value for the error type of the data operation error is determined. The first non-volatile memory die is marked for exclusion from subsequent data operations.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: October 22, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: Sanghoon Chu, Scott Jinn, Yuriy Pavlenko, Kum-Jung Song
  • Patent number: 10453548
    Abstract: The subject technology provides implementations, which may be included as part of firmware of the flash memory device, that will not solely rely on a flash controller interpreted status but includes additional checks to the returned flash status byte. Each flash read, write, and erase command requires a status read command to determine the state of operation. Depending on the particular command issued, each bit of the returned status has a different meaning. The flash memory device firmware can check whether an illogical or inconsistent status is present. For example, if an overall pass/fail bit indicates a “pass” but a plane pass/fail bit indicates a “fail” then there could be an erroneous detection. Also, for every operation, the firmware can read status twice when the flash memory is ready. If the second status byte fails to match the first status byte then a die may be flagged as failing.
    Type: Grant
    Filed: May 19, 2017
    Date of Patent: October 22, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: Sanghoon Chu, Scott Jinn, Yuriy Pavlenko
  • Publication number: 20190317678
    Abstract: Command scheduling for die sets of non-volatile memory may be performed based on command states of the die sets. Upon receiving an erase command to erase data stored in a first block set of non-volatile memory, a command state of the first die set of the non-volatile memory is determined, where the first die set contains the first block set. If the first die set is determined to be in a pending command state, the erase command is queued in a wait queue. If the first die set is determined to be in an idle command state, the erase command is scheduled to erase the data stored in the first block set.
    Type: Application
    Filed: June 27, 2019
    Publication date: October 17, 2019
    Inventors: YungLi JI, Yun-Tzuo LAI, Haining LIU, Yuriy PAVLENKO
  • Patent number: 10379765
    Abstract: Command scheduling for die sets of non-volatile memory may be performed based on command states of the die sets. Upon receiving an erase command to erase data stored in a first block set of non-volatile memory, a command state of the first die set of the non-volatile memory is determined, where the first die set contains the first block set. If the first die set is determined to be in a pending command state, the erase command is queued in a wait queue. If the first die set is determined to be in an idle command state, the erase command is scheduled to erase the data stored in the first block set.
    Type: Grant
    Filed: August 15, 2017
    Date of Patent: August 13, 2019
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: YungLi Ji, Yun-Tzuo Lai, Haining Liu, Yuriy Pavlenko
  • Patent number: 10379979
    Abstract: A device that provides power fail handling using command suspension includes non-volatile memory circuits and a controller that is configured to determine that a power fail event has occurred. The controller is configured to determine, in response to the determination that the power fail event has occurred, which of the non-volatile memory circuits are executing a first type of memory commands. The controller is also configured to issue a stop command to the determined non-volatile memory circuits to stop execution of the first type of memory commands.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: August 13, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: YungLi Ji, Yuriy Pavlenko, Kum-Jung Song
  • Publication number: 20190227720
    Abstract: A storage device may include a controller and a memory array including a plurality of dies arranged into a plurality of channels. In some examples, the controller may be configured to define, from the memory array, a plurality of die-sets based on respective chip enable lines associated with the plurality of dies, wherein each die-set of the plurality of die-sets includes at least one die from each of the plurality of channels; define, from a selected die-set of the plurality of die-sets, a plurality of blocksets, wherein each blockset includes a block from each die of the selected die-set; receive a unit of data to be stored; and issue commands that cause the unit of data to be stored in blocks of a selected blockset of the plurality of blocksets.
    Type: Application
    Filed: March 29, 2019
    Publication date: July 25, 2019
    Inventors: Haining LIU, Yuriy PAVLENKO, George G. Artnak, JR.
  • Patent number: 10289314
    Abstract: A storage device may include a controller and a memory array including a plurality of dies arranged into a plurality of channels. In some examples, the controller may be configured to define, from the memory array, a plurality of die-sets based on respective chip enable lines associated with the plurality of dies, wherein each die-set of the plurality of die-sets includes at least one die from each of the plurality of channels; define, from a selected die-set of the plurality of die-sets, a plurality of blocksets, wherein each blockset includes a block from each die of the selected die-set; receive a unit of data to be stored; and issue commands that cause the unit of data to be stored in blocks of a selected blockset of the plurality of blocksets.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: May 14, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: Haining Liu, Yuriy Pavlenko, George G. Artnak, Jr.
  • Publication number: 20180373450
    Abstract: Command scheduling for die sets of non-volatile memory may be performed based on command states of the die sets. Upon receiving an erase command to erase data stored in a first block set of non-volatile memory, a command state of the first die set of the non-volatile memory is determined, where the first die set contains the first block set. If the first die set is determined to be in a pending command state, the erase command is queued in a wait queue. If the first die set is determined to be in an idle command state, the erase command is scheduled to erase the data stored in the first block set.
    Type: Application
    Filed: August 15, 2017
    Publication date: December 27, 2018
    Inventors: YUNGLI JI, YUN-TZUO LAI, HAINING LIU, YURIY PAVLENKO
  • Publication number: 20180349240
    Abstract: A device that provides power fail handling using command suspension includes non-volatile memory circuits and a controller that is configured to determine that a power fail event has occurred. The controller is configured to determine, in response to the determination that the power fail event has occurred, which of the non-volatile memory circuits are executing a first type of memory commands. The controller is also configured to issue a stop command to the determined non-volatile memory circuits to stop execution of the first type of memory commands.
    Type: Application
    Filed: May 31, 2017
    Publication date: December 6, 2018
    Inventors: YungLi JI, Yuriy PAVLENKO, Kum-Jung SONG