Patents by Inventor Yusaku ASANO
Yusaku ASANO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10422930Abstract: An optical element includes a first surface and a second surface opposite to the first surface, and includes a first region. A refractive index of the first region is asymmetric with respect to a first axis. The first axis passes through a first position and is parallel to a first thickness direction. The first refractive index is highest or lowest at the first position in the first region. The first thickness direction is from the first surface toward the second surface in the first region.Type: GrantFiled: September 1, 2014Date of Patent: September 24, 2019Assignee: Kabushiki Kaisha ToshibaInventor: Yusaku Asano
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Patent number: 10410976Abstract: A method of manufacturing a semiconductor chip according to an embodiment includes forming on a semiconductor substrate a plurality of etching masks each including a protection film to demarcate a plurality of first regions of the substrate protected by the plurality of etching masks and a second region as an exposed region of the substrate, and anisotropically removing the second region by a chemical etching process to form a plurality of grooves each including a side wall at least partially located in the same plane as an end face of the etching mask and a bottom portion reaching a back surface of the substrate, thereby singulating the semiconductor substrate into a plurality of chip main bodies corresponding to the plurality of first regions.Type: GrantFiled: August 18, 2016Date of Patent: September 10, 2019Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Yusaku Asano, Kazuhito Higuchi, Taizo Tomioka, Tomohiro Iguchi
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Patent number: 10233557Abstract: An electroplating method according to an embodiment is a electroplating method of generating a metal film on a cathode surface by setting a negative potential to a cathode of an anode and the cathode provided in a reaction bath, including mixing and accommodating a plating solution containing at least plated metal ions, an electrolyte, and a surface active agent and a supercritical fluid in the reaction bath and applying a current in a concentration of the supercritical fluid and a cathode current density in which a polarization resistance obtained from a cathode polarization curve while the plated metal ions are reduced is larger than before the supercritical fluid is mixed.Type: GrantFiled: March 9, 2016Date of Patent: March 19, 2019Assignees: KABUSHIKI KAISHA TOSHIBA, TOKYO INSTITUTE OF TECHNOLOGYInventors: Kazuhito Higuchi, Yusaku Asano, Kyoko Honma, Kazuma Hiraguri, Yasunari Ukita, Masayuki Uchida, Toshiya Nakayama, Mayumi Machino, Masato Sone, Tso-Fu Mark Chang
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Patent number: 10224209Abstract: An etching method according to an embodiment includes supplying an etchant containing hydrofluoric acid, an oxidizer, and a buffer to a semiconductor substrate including a first region covered with a metal layer made of one or more metals other than noble metals, and a second region covered with a catalyst layer made of a noble metal, such that the etchant comes in contact with the catalyst layer and the metal layer, thereby etching the semiconductor substrate at a position of the catalyst layer.Type: GrantFiled: July 22, 2016Date of Patent: March 5, 2019Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Keiichiro Matsuo, Yusaku Asano
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Patent number: 10090158Abstract: An etching method according to an embodiment includes forming a catalyst layer made of a first noble metal or the combination of the second noble metal and the metal other than noble metals on a surface made of a semiconductor, the catalyst layer including a first portion and a second portion, the first portion covering at least a part of the surface, the second portion being located on the first portion, having an apparent density lower than that of the first portion, and being thicker than the first portion; and supplying an etchant to the catalyst layer to cause an etching of the surface with an assist from the catalyst layer as a catalyst.Type: GrantFiled: July 25, 2017Date of Patent: October 2, 2018Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Keiichiro Matsuo, Yusaku Asano, Kazuhito Higuchi, Kazuo Shimokawa
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Publication number: 20180033634Abstract: An etching method according to an embodiment includes forming a catalyst layer made of a first noble metal or the combination of the second noble metal and the metal other than noble metals on a surface made of a semiconductor, the catalyst layer including a first portion and a second portion, the first portion covering at least a part of the surface, the second portion being located on the first portion, having an apparent density lower than that of the first portion, and being thicker than the first portion; and supplying an etchant to the catalyst layer to cause an etching of the surface with an assist from the catalyst layer as a catalyst.Type: ApplicationFiled: July 25, 2017Publication date: February 1, 2018Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Keiichiro MATSUO, Yusaku Asano, Kazuhito Higuchi, Kazuo Shimokawa
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Publication number: 20170267926Abstract: Disclosed herein is an etching solution containing hydrofluoric acid, an oxidizer, and an organic additive, wherein the organic additive is one or more compounds selected from polyethylene glycol, succinic acid, malic acid, dipropylamine, and alanine. This disclosure also includes an etching solution that removes a portion of a structure made of a semiconductor that is in contact with a catalyst layer made of a noble metal.Type: ApplicationFiled: June 2, 2017Publication date: September 21, 2017Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Yusaku ASANO
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Patent number: 9701902Abstract: An etching method according to an embodiment includes forming a catalyst layer made of a noble metal on a structure made of a semiconductor, and dipping the structure in an etching solution containing hydrofluoric acid, an oxidizer, and an organic additive to remove a portion of the structure that is in contact with the catalyst layer.Type: GrantFiled: September 4, 2015Date of Patent: July 11, 2017Assignee: KABUSHIKI KAISHA TOSHIBAInventor: Yusaku Asano
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Publication number: 20170075041Abstract: An optical element includes a first surface and a second surface opposite to the first surface, and includes a first region. A refractive index of the first region is asymmetric with respect to a first axis. The first axis passes through a first position and is parallel to a first thickness direction. The first refractive index is highest or lowest at the first position in the first region. The first thickness direction is from the first surface toward the second surface in the first region.Type: ApplicationFiled: September 1, 2014Publication date: March 16, 2017Applicant: Kabushiki Kaisha ToshibaInventor: Yusaku ASANO
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Publication number: 20170076982Abstract: Provided is a device manufacturing method according to an embodiment including forming a film on a second plane side of a substrate having a first plane and the second plane, forming grooves on the substrate from the first plane side so that the film remains, and performing an ultrasonic process on the substrate in a liquid to remove the film of the second plane side at positions where the grooves are formed.Type: ApplicationFiled: February 23, 2016Publication date: March 16, 2017Inventors: Seiya Sakakura, Masamune Takano, Yusaku Asano, Keiichiro Matsuo
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Publication number: 20170062230Abstract: An etching method according to an embodiment includes supplying an etchant containing hydrofluoric acid, an oxidizer, and a buffer to a semiconductor substrate including a first region covered with a metal layer made of one or more metals other than noble metals, and a second region covered with a catalyst layer made of a noble metal, such that the etchant comes in contact with the catalyst layer and the metal layer, thereby etching the semiconductor substrate at a position of the catalyst layer.Type: ApplicationFiled: July 22, 2016Publication date: March 2, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Keiichiro MATSUO, Yusaku ASANO
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Publication number: 20160358863Abstract: A method of manufacturing a semiconductor chip according to an embodiment includes forming on a semiconductor substrate a plurality of etching masks each including a protection film to demarcate a plurality of first regions of the substrate protected by the plurality of etching masks and a second region as an exposed region of the substrate, and anisotropically removing the second region by a chemical etching process to form a plurality of grooves each including a side wall at least partially located in the same plane as an end face of the etching mask and a bottom portion reaching a back surface of the substrate, thereby singulating the semiconductor substrate into a plurality of chip main bodies corresponding to the plurality of first regions.Type: ApplicationFiled: August 18, 2016Publication date: December 8, 2016Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yusaku ASANO, Kazuhito HIGUCHI, Taizo TOMIOKA, Tomohiro IGUCHI
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Patent number: 9460967Abstract: A method of manufacturing a semiconductor chip according to an embodiment includes forming on a semiconductor substrate a plurality of etching masks each including a protection film to demarcate a plurality of first regions of the substrate protected by the plurality of etching masks and a second region as an exposed region of the substrate, and anisotropically removing the second region by a chemical etching process to form a plurality of grooves each including a side wall at least partially located in the same plane as an end face of the etching mask and a bottom portion reaching a back surface of the substrate, thereby singulating the semiconductor substrate into a plurality of chip main bodies corresponding to the plurality of first regions.Type: GrantFiled: November 13, 2014Date of Patent: October 4, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Yusaku Asano, Kazuhito Higuchi, Taizo Tomioka, Tomohiro Iguchi
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Publication number: 20160273121Abstract: An electroplating method according to an embodiment is a electroplating method of generating a metal film on a cathode surface by setting a negative potential to a cathode of an anode and the cathode provided in a reaction bath, including mixing and accommodating a plating solution containing at least plated metal ions, an electrolyte, and a surface active agent and a supercritical fluid in the reaction bath and applying a current in a concentration of the supercritical fluid and a cathode current density in which a polarization resistance obtained from a cathode polarization curve while the plated metal ions are reduced is larger than before the supercritical fluid is mixed.Type: ApplicationFiled: March 9, 2016Publication date: September 22, 2016Applicants: KABUSHIKI KAISHA TOSHIBA, TOKYO INSTITUTE OF TECHNOLOGYInventors: Kazuhito HIGUCHI, Yusaku Asano, Kyoko Honma, Kazuma Hiraguri, Yasunari Ukita, Masayuki Uchida, Toshiya Nakayama, Mayumi Machino, Masato Sone, Tso-Fu Mark Chang
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Publication number: 20160079078Abstract: An etching method according to an embodiment includes forming a catalyst layer made of a noble metal on a structure made of a semiconductor, and dipping the structure in an etching solution containing hydrofluoric acid, an oxidizer, and an organic additive to remove a portion of the structure that is in contact with the catalyst layer.Type: ApplicationFiled: September 4, 2015Publication date: March 17, 2016Applicant: Kabushiki Kaisha ToshibaInventor: Yusaku ASANO
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Patent number: 9274017Abstract: According to one embodiment, a MEMS device is disclosed. The device includes a substrate, a first and second MEMS elements on the substrate. Each of the first and second MEMS elements includes a fixed electrode on the substrate, a movable electrode above the fixed electrode, a first insulating film, the first insulating film and the substrate defining a cavity in which the fixed and movable electrodes are contained, and a first anchor on a surface of the first insulating film inside the cavity and configured to connect the movable electrode to the first insulating film. The cavity of the first MEMS element is closed. The cavity of the second MEMS element is opened by a through hole.Type: GrantFiled: February 24, 2014Date of Patent: March 1, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Naofumi Nakamura, Kei Masunishi, Yumi Hayashi, Yusaku Asano, Tamio Ikehashi, Jun Deguchi, Daiki Ono
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Publication number: 20150130028Abstract: A method of manufacturing a semiconductor chip according to an embodiment includes forming on a semiconductor substrate a plurality of etching masks each including a protection film to demarcate a plurality of first regions of the substrate protected by the plurality of etching masks and a second region as an exposed region of the substrate, and anisotropically removing the second region by a chemical etching process to form a plurality of grooves each including a side wall at least partially located in the same plane as an end face of the etching mask and a bottom portion reaching a back surface of the substrate, thereby singulating the semiconductor substrate into a plurality of chip main bodies corresponding to the plurality of first regions.Type: ApplicationFiled: November 13, 2014Publication date: May 14, 2015Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yusaku ASANO, Kazuhito Higuchi, Taizo Tomioka, Tomohiro Iguchi
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Patent number: 9000547Abstract: According to one embodiment, a strain sensor includes a substrate, a lid, a frame, and a sensing unit. The substrate has a first surface. The lid is provided on the first surface. The frame is provided between the substrate and the lid. The frame is nonconductive and includes a magnetic body. The sensing unit is provided inside the frame between the substrate and the lid, and includes a magnetoresistance effect element.Type: GrantFiled: March 11, 2014Date of Patent: April 7, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Yusaku Asano, Kazuhito Higuchi, Takeshi Miyagi, Yoshihiro Higashi, Michiko Hara, Hideaki Fukuzawa, Masayuki Kii, Eizo Fujisawa
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Publication number: 20150069540Abstract: According to one embodiment, a strain sensor includes a substrate, a lid, a frame, and a sensing unit. The substrate has a first surface. The lid is provided on the first surface. The frame is provided between the substrate and the lid. The frame is nonconductive and includes a magnetic body. The sensing unit is provided inside the frame between the substrate and the lid, and includes a magnetoresistance effect element.Type: ApplicationFiled: March 11, 2014Publication date: March 12, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Yusaku ASANO, Kazuhito HIGUCHI, Takeshi MIYAGI, Yoshihiro HIGASHI, Michiko HARA, Hideaki FUKUZAWA, Masayuki KII, Eizo FUJISAWA
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Publication number: 20150068314Abstract: According to one embodiment, a MEMS device is disclosed. The device includes a substrate, a first and second MEMS elements on the substrate. Each of the first and second MEMS elements includes a fixed electrode on the substrate, a movable electrode above the fixed electrode, a first insulating film, the first insulating film and the substrate defining a cavity in which the fixed and movable electrodes are contained, and a first anchor on a surface of the first insulating film inside the cavity and configured to connect the movable electrode to the first insulating film. The cavity of the first MEMS element is closed. The cavity of the second MEMS element is opened by a through hole.Type: ApplicationFiled: February 24, 2014Publication date: March 12, 2015Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Naofumi NAKAMURA, Kei MASUNISHI, Yumi HAYASHI, Yusaku ASANO, Tamio IKEHASHI, Jun DEGUCHI, Daiki ONO