Abstract: Structures for a wavelength division multiplexing filter and methods of fabricating a structure for a wavelength division multiplexing filter. The structure includes a first waveguide core having a first section and a second section. The first section and the second section have a first notched sidewall and a second notched sidewall opposite to the first notched sidewall. The structure further includes a second waveguide core positioned with a first offset in a first direction relative to the first section and the second section of the first waveguide core and with a second offset in a second direction relative to the first section and the second section of the first waveguide core. The second direction is transverse to the first direction.

Abstract: A photonic integrated circuit (PIC) die are provided. The PIC die includes a set of optical connect grooves including a first groove aligning a core of a first optical fiber positioned with a first optical component in a first layer at a first vertical depth in a plurality of layers of a body of the die, and a second groove aligning a core of a second optical fiber positioned therein with a second optical component in a second, different layer at a second different vertical depth in the plurality of layers. The grooves may also have end faces at different lateral depths from an edge of the body of the PIC die. Any number of the first and second grooves can be used to communicate an optical signal to any number of layers at different vertical and/or lateral depths within the body of the PIC die.

Abstract: Structures for an edge coupler and methods of forming a structure for an edge coupler. The structure includes a waveguide core over a dielectric layer, and a back-end-of-line stack over the waveguide core and the dielectric layer. The back-end-of-line stack includes an interlayer dielectric layer, a side edge, a first feature, a second feature, and a third feature laterally arranged between the first feature and the second feature. The first feature, the second feature, and the third feature are positioned on the interlayer dielectric layer adjacent to the side edge, and the third feature has an overlapping relationship with a tapered section of the waveguide core.

Abstract: A photonic integrated circuit (PIC) die includes a silicon nitride optical component over an active region. Multiple interconnect layers are over the silicon nitride optical component, each of the multiple interconnect layers including a metal interconnect therein. At least one optical deflector is over the multiple interconnect layers and over the silicon nitride optical component. The optical deflector(s) may also include a contact passing therethrough to the interconnect layers, but do not include any other electrical interconnects. Each optical deflector may deflect light within an ambient light range of less than 570 nanometers (nm) to protect the silicon nitride optical component from light-induced degradation.

Abstract: Structures including an edge coupler and methods of fabricating a structure including an edge coupler. The structure includes a first waveguide core having a first inverse taper, a second waveguide core having a second inverse taper, and a third waveguide core having a third inverse taper that is laterally positioned between the first inverse taper and the second inverse taper. The structure further includes a fourth waveguide core having a fourth inverse taper that is positioned to overlap with the first inverse taper, and a fifth waveguide core having a fifth inverse taper that is positioned to overlap with the second inverse taper.

Abstract: Embodiments of the disclosure provide an optical polarizer with a varying vertical thickness, and methods to form the same. An optical polarizer according to the disclosure may include a first waveguide core over a semiconductor substrate. A first cladding material is on at least an upper surface of the first waveguide core. A second waveguide core over the first waveguide core and above the first cladding material. The second waveguide core includes a first segment having a vertical thickness that varies along a length of the first segment. A second cladding material is at least partially surrounding the second waveguide core. Transfer of one of a transverse electric (TE) mode signal and a transverse magnetic (TM) mode signal from the first waveguide core to the second waveguide core occurs between the first segment of the second waveguide core and the first waveguide core.

Abstract: Disclosed are embodiments of a photonic integrated circuit (PIC) structure with a waveguide core having tapered sidewall liner(s) (e.g., symmetric tapered sidewall liners on opposing sides of a waveguide core, asymmetric tapered sidewall liners on opposing sides of a waveguide core, or a tapered sidewall liner on one side of a waveguide core). In some embodiments, the tapered sidewall liner(s) and waveguide core have different refractive indices. In an exemplary embodiment, the waveguide core is a first material (e.g., silicon) and the tapered sidewall liner(s) is/are a second material (e.g., silicon nitride) with a smaller refractive index than the first material. In another exemplary embodiment, the waveguide core is a first compound and the tapered sidewall liner(s) is/are a second compound with the same elements (e.g., silicon and nitrogen) as the first compound but with a smaller refractive index. Also disclosed are method embodiments for forming such a PIC structure.

Abstract: Embodiments of the disclosure provide an optical ring modulator. The optical ring modulator includes waveguide with a first semiconductor material of a first doping type, and a second semiconductor material having a second doping type adjacent the first semiconductor material. A P-N junction is between the first semiconductor material and the second semiconductor material. A plurality of photonic crystal layers, each embedded within the first semiconductor material or the second semiconductor material, has an upper surface that is substantially coplanar with an upper surface of the waveguide structure.

Abstract: Structures for a photodetector or terminator and methods of fabricating a structure for a photodetector or terminator. The structure includes a waveguide core having a longitudinal axis, a pad connected to the waveguide core, and a light-absorbing layer on the pad adjacent to the waveguide core. The light-absorbing layer includes an annular portion, a first taper, and a second taper laterally spaced from the first taper. The first taper and the second taper are positioned adjacent to the waveguide core.

Abstract: Structures including an optical coupler and methods of fabricating a structure including an optical coupler. The structure includes a substrate, a first dielectric layer on the substrate, and an optical coupler having a first grating and a second grating. The first grating has a first plurality of segments positioned in a first level over the first dielectric layer. The second grating has a second plurality of segments positioned in a second level over the first dielectric layer. The second level differs in elevation above the first dielectric layer from the first level. The second plurality of segments are positioned in the second level to overlap with the first plurality of segments of the first grating, and the second plurality of segments comprise a metal. A second dielectric layer is positioned in a vertical direction between the first level and the second level.

Abstract: Structures including an optical coupler and methods of fabricating a structure including an optical coupler. The structure includes a substrate, a first dielectric layer on the substrate, and an optical coupler having a first grating and a second grating. The first grating has a first plurality of segments positioned in a first level over the first dielectric layer. The second grating has a second plurality of segments positioned in a second level over the first dielectric layer. The second level differs in elevation above the first dielectric layer from the first level. The second plurality of segments are positioned in the second level to overlap with the first plurality of segments of the first grating, and the second plurality of segments comprise a metal. A second dielectric layer is positioned in a vertical direction between the first level and the second level.

Abstract: Disclosed is a photonic structure and associated method. The structure includes a closed-curve waveguide having a first height, as measured from the top surface of an insulator layer, and an outer curved sidewall that extends essentially vertically the full first height (e.g., to minimize signal loss). The structure includes a closed-curve thermal coupler and a heating element. The closed-curve thermal coupler is thermally coupled to and laterally surrounded by the closed-curve waveguide and has a second height that is less than the first height. In some embodiments, the closed-curve waveguide and the closed-curve thermal coupler are continuous portions of the same semiconductor layer having different thicknesses. The heating element is thermally coupled to the closed-curve thermal coupler and thereby indirectly thermally coupled to the closed-curve waveguide.

Abstract: Disclosed is a photonic integrated circuit (PIC) structure including: a first waveguide with a first main body and a first end portion, which is tapered; and a second waveguide with a second main body and a second end portion, which has two branch waveguides that are positioned adjacent to opposing sides, respectively, of the first end portion of the first waveguide and that branch out from the second main body, thereby forming a V, U or similar shape. The arrangement of the two branch waveguides of the second end portion of the second waveguide relative to the tapered first end portion of the first waveguide allows for mode matching conditions to be met at multiple locations at the interface between the waveguides, thereby creating multiple signal paths between the waveguides and effectively reducing the light signal power density along any one path to prevent or at least minimize any power-induced damage.

Abstract: Disclosed is a photonic integrated circuit (PIC) structure including: a first primary waveguide, which has a first main body and a first end portion that is tapered; at least one supplemental waveguide positioned laterally adjacent to and extending beyond the first end portion of the first primary waveguide; and a second primary waveguide, which has a second main body and a second end portion that at least partially underlays/overlays the first end portion of the first primary waveguide and the supplemental waveguide(s). The arrangement the end portions of the primary waveguides and the supplemental waveguide(s) allows for mode matching conditions to be met at multiple locations at the interface between the primary waveguides, thereby creating multiple signal paths between the primary waveguides and effectively reducing the light signal power density in any one path to prevent or at least minimize any power-induced damage.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to non-planar waveguide structures and methods of manufacture. The structure includes: a first waveguide structure; and a non-planar waveguide structure spatially shifted from the first waveguide structure and separated from the first waveguide structure by an insulator material.

Abstract: Structures for a photodetector and methods of fabricating a structure for a photodetector. A photodetector includes a photodetector pad coupled to a waveguide core and a light-absorbing layer coupled to the photodetector pad. The light-absorbing layer has a body, a first taper that projects laterally from the body toward the waveguide core, and a second taper that projects laterally from the body toward the waveguide core. The photodetector pad includes a tapered section that is laterally positioned between the first taper and the second taper of the light-absorbing layer.

Abstract: Structures for a photonics chip that include a fully-depleted silicon-on-insulator field-effect transistor and related methods. A first device region of a substrate includes a first device layer, a first portion of a second device layer, and a buried insulator layer separating the first device layer from the first portion of the second device layer. A second device region of the substrate includes a second portion of the second device layer. The first device layer, which has a thickness in a range of about 4 to about 20 nanometers, transitions in elevation to the second portion of the second device layer with a step height equal to a sum of the thicknesses of the first device layer and the buried insulator layer. A field-effect transistor includes a gate electrode on the top surface of the first device layer. An optical component includes the second portion of the second device layer.

Abstract: Embodiments of the disclosure provide an optical antenna for a photonic integrated circuit (PIC). The optical antenna includes a vertically oriented semiconductor waveguide with a first end on a semiconductor layer. The vertically oriented semiconductor waveguide includes a first sidewall and a second sidewall opposite the first sidewall. A reflective material is along the second sidewall of the vertically oriented semiconductor waveguide. A first plurality of grating protrusions extends from the first sidewall of the vertically oriented semiconductor waveguide.

Abstract: Structures for a photonics chip that include a fully-depleted silicon-on-insulator field-effect transistor and related methods. A first device region of a substrate includes a first device layer, a first portion of a second device layer, and a buried insulator layer separating the first device layer from the first portion of the second device layer. A second device region of the substrate includes a second portion of the second device layer. The first device layer, which has a thickness in a range of about 4 to about 20 nanometers, transitions in elevation to the second portion of the second device layer with a step height equal to a sum of the thicknesses of the first device layer and the buried insulator layer. A field-effect transistor includes a gate electrode on the top surface of the first device layer. An optical component includes the second portion of the second device layer.

Abstract: Structures for a photonics chip that include a fully-depleted silicon-on-insulator field-effect transistor and related methods. A first device region of a substrate includes a first device layer, a first portion of a second device layer, and a buried insulator layer separating the first device layer from the first portion of the second device layer. A second device region of the substrate includes a second portion of the second device layer. The first device layer, which has a thickness in a range of about 4 to about 20 nanometers, transitions in elevation to the second portion of the second device layer with a step height equal to a sum of the thicknesses of the first device layer and the buried insulator layer. A field-effect transistor includes a gate electrode on the top surface of the first device layer. An optical component includes the second portion of the second device layer.