Patents by Inventor Yusuke ARAYASHIKI

Yusuke ARAYASHIKI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130228736
    Abstract: According to one embodiment, a memory device includes a first electrode, a second electrode, and a variable resistance film. The variable resistance film is connected between the first electrode and the second electrode. The first electrode includes a metal contained in a matrix made of a conductive material. A cohesive energy of the metal is lower than a cohesive energy of the conductive material. A concentration of the metal at a central portion of the first electrode in a width direction thereof is higher than concentrations of the metal in two end portions of the first electrode in the width direction.
    Type: Application
    Filed: August 30, 2012
    Publication date: September 5, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Daisuke MATSUSHITA, Shosuke Fujii, Yoshifumi Nishi, Akira Takashima, Takayuki Ishikawa, Hidenori Miyagawa, Takashi Haimoto, Yusuke Arayashiki, Hideki Inokuma
  • Patent number: 8476128
    Abstract: A CMOSFET is composed of a P-channel MOSFET and an N-channel MOSFET formed on a silicon substrate. The P-channel MOSFET is formed a first gate insulating film, a first hafnium layer and a first gate electrode which are stacked on the silicon substrate. The N-channel MOSFET is formed a second gate insulating film, a second hafnium layer and a second gate electrode which are stacked on the silicon substrate. A surface density of the second hafnium layer is lower than a surface density of the first hafnium layer.
    Type: Grant
    Filed: January 5, 2010
    Date of Patent: July 2, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yusuke Arayashiki
  • Publication number: 20130161582
    Abstract: According to one embodiment, a conductive bridging memory device includes a first wiring layer having a plurality of first wiring portions extending in a first direction, a second wiring layer having a plurality of second wiring portions extending in a second direction crossing the first direction, and a resistance change layer provided continuously along a plane having the first direction and the second direction between the first wiring layer and the second wiring layer. Each of the first wiring portions includes a first wiring extending in the first direction. Each of the second wiring portions includes a second wiring extending in the second direction, and an ion metal layer provided between the second wiring and the resistance change layer and extending in the second direction.
    Type: Application
    Filed: August 28, 2012
    Publication date: June 27, 2013
    Inventor: Yusuke ARAYASHIKI
  • Publication number: 20110244649
    Abstract: A method of manufacturing a semiconductor device includes: a process to form an element isolation trench on a semiconductor substrate, the element isolation trench having a crystal plane orientation that is different from a crystal plane orientation on a surface of the semiconductor substrate; a process to deposit, on the semiconductor substrate, one of a metal that promotes generation of oxygen radicals and a metal containing film that promotes generation of the oxygen radicals; a process to oxidize the semiconductor substrate; and a process to remove the one of the metal and the metal containing film.
    Type: Application
    Filed: March 30, 2011
    Publication date: October 6, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takashi SHIMIZU, Yusuke Arayashiki
  • Publication number: 20110187912
    Abstract: A solid state imaging device according to an embodiment includes a light sensing part which conducts photoelectric conversion on incident light. The solid state imaging device includes a ferroelectric layer including an organic compound on a surface of the light sensing part on which light is incident. The solid state imaging device includes a transparent electrode formed on the ferroelectric layer.
    Type: Application
    Filed: January 31, 2011
    Publication date: August 4, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yusuke ARAYASHIKI, Kazuaki Nakajima
  • Publication number: 20100176455
    Abstract: A CMOSFET is composed of a P-channel MOSFET and an N-channel MOSFET formed on a silicon substrate. The P-channel MOSFET is formed a first gate insulating film, a first hafnium layer and a first gate electrode which are stacked on the silicon substrate. The N-channel MOSFET is formed a second gate insulating film, a second hafnium layer and a second gate electrode which are stacked on the silicon substrate. A surface density of the second hafnium layer is lower than a surface density of the first hafnium layer.
    Type: Application
    Filed: January 5, 2010
    Publication date: July 15, 2010
    Inventor: Yusuke ARAYASHIKI