Patents by Inventor Yusuke Higashi
Yusuke Higashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11971045Abstract: A drive support unit of a turbo compressor includes at least one bearingless motor. The at least one bearingless motor includes a rotor-stator pair constituted by a rotor and a stator, and is configured to rotationally drive a drive shaft and to support a radial load of the drive shaft in a contactless manner. Accordingly, it is possible to provide a turbo compressor to which a bearingless motor is applied.Type: GrantFiled: May 8, 2018Date of Patent: April 30, 2024Assignee: Daikin Industries, Ltd.Inventors: Yuji Nakazawa, Atsushi Sakawaki, Hirofumi Higashi, Taiichi Nose, Takaaki Ono, Yusuke Irino
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Publication number: 20230320093Abstract: A semiconductor memory device according to an embodiment includes a stacked body in which a gate electrode layer and a first insulating layer are alternately stacked in a first direction, a semiconductor layer in the stacked body and extending in the first direction, a second insulating layer between the semiconductor layer and the stacked body, a third insulating layer provided between the second insulating layer and the stacked body, and a first layer between the second insulating layer and the third insulating layer. The first layer contains silicon and nitrogen and includes a first region between the gate electrode layer and the semiconductor layer and a second region between the first insulating layer and the semiconductor layer, the first region contains or does not contain fluorine, the second region contains fluorine, and a fluorine concentration of the second region is higher than a fluorine concentration of the first region.Type: ApplicationFiled: September 2, 2022Publication date: October 5, 2023Applicant: Kioxia CorporationInventors: Harumi SEKI, Masamichi SUZUKI, Reika TANAKA, Kensuke OTA, Yusuke HIGASHI
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Patent number: 11380773Abstract: A semiconductor memory device of an embodiment includes a semiconductor layer; a gate electrode including a first portion, a second portion provided to be spaced apart from the first portion, and a spacer provided between the first portion and the second portion; and a first insulating layer provided between the semiconductor layer and the gate electrode and including a first region containing a ferroelectric, a ferrielectric, or an anti-ferroelectric, a second region containing a ferroelectric, a ferrielectric, or an anti-ferroelectric, and a boundary region provided between the first region and the second region. The first region is positioned between the first portion and the semiconductor layer, the second region is positioned between the second portion and the semiconductor layer, the boundary region is positioned between the spacer and the semiconductor layer, and the boundary region has a chemical composition different from that of the spacer.Type: GrantFiled: October 31, 2019Date of Patent: July 5, 2022Assignee: Kioxia CorporationInventors: Tsunehiro Ino, Yusuke Higashi, Toshinori Numata, Yuuichi Kamimuta
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Publication number: 20210072572Abstract: A light control device including a light control sheet including a light control layer switchable between at least a first state and a second state by changing alignment of liquid crystal molecules by application of a drive voltage, and transparent electrode layers sandwiching the light control layer. The light control layer is transparent in the first state and turbid in the second state. The light control layer is in the second state when there is no application of the drive voltage. When the light control layer is in the second state, the light control sheet has a transmitted image definition of 70% or less, where the transmitted image definition is based on JIS K 7374:2007 with an optical comb width set to 0.125 mm.Type: ApplicationFiled: November 16, 2020Publication date: March 11, 2021Applicant: TOPPAN PRINTING CO., LTD.Inventors: Takehiro YAMADA, Yusuke HIGASHI
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Patent number: 10872900Abstract: An example semiconductor device includes: n conductive layers including first to nth conductive layers stacked in a first direction; a first semiconductor region of a first conductive type; a second semiconductor region of a second conductive type closer to the nth conductive layer than the first semiconductor region; a semiconductor layer provided between the first semiconductor region and the second semiconductor region, extending in the first direction, penetrating the n conductive layers, and having an impurity concentration lower than a first conductive impurity concentration of the first region and a second conductive impurity concentration of the second region; n charge storage regions including first to nth charge storage regions provided between the n conductive layers and the semiconductor layer, and a control circuit that controls a voltage applied to the n conductive layers to always prevent charges from being stored in at least one of the n charge storage regions.Type: GrantFiled: February 22, 2019Date of Patent: December 22, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Tomoya Sanuki, Yusuke Higashi, Hideto Horii, Masaki Kondo, Hiroki Tokuhira, Hideaki Aochi
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Patent number: 10861528Abstract: A semiconductor memory device according to one embodiment includes: a memory cell, the memory cell including a ferroelectric film; and a control circuit controlling the memory cell. Additionally, the control circuit determining whether the number of times of executions of a write process or an erase process on the memory cell has reached a predetermined number of times; and, if the number of times of executions has reached the predetermined number of times, executing a voltage application process in which a first voltage of a first polarity and a second voltage of a second polarity opposite to the first polarity are applied to the ferroelectric film.Type: GrantFiled: March 26, 2020Date of Patent: December 8, 2020Assignee: Toshiba Memory CorporationInventors: Yusuke Higashi, Yuuichi Kamimuta, Tsunehiro Ino
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Publication number: 20200227108Abstract: A semiconductor memory device according to one embodiment includes: a memory cell, the memory cell including a ferroelectric film; and a control circuit controlling the memory cell. Additionally, the control circuit determining whether the number of times of executions of a write process or an erase process on the memory cell has reached a predetermined number of times; and, if the number of times of executions has reached the predetermined number of times, executing a voltage application process in which a first voltage of a first polarity and a second voltage of a second polarity opposite to the first polarity are applied to the ferroelectric film.Type: ApplicationFiled: March 26, 2020Publication date: July 16, 2020Applicant: Toshiba Memory CorporationInventors: Yusuke Higashi, Yuuichi Kamimuta, Tsunehiro Ino
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Patent number: 10636468Abstract: A semiconductor memory device according to one embodiment includes: a memory cell, the memory cell including a ferroelectric film; and a control circuit controlling the memory cell. Additionally, the control circuit determining whether the number of times of executions of a write process or an erase process on the memory cell has reached a predetermined number of times; and, if the number of times of executions has reached the predetermined number of times, executing a voltage application process in which a first voltage of a first polarity and a second voltage of a second polarity opposite to the first polarity are applied to the ferroelectric film.Type: GrantFiled: August 27, 2018Date of Patent: April 28, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Yusuke Higashi, Yuuichi Kamimuta, Tsunehiro Ino
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Patent number: 10607701Abstract: According to one embodiment, a semiconductor storage device includes: a first select transistor connected at a first end of a memory string; a second select transistor connected at a second end of the memory string; and a controller. In a write operation of writing data into a first memory cell transistor of the memory string, the controller performs: a first operation of applying a first voltage to a gate of the first memory cell transistor, while turning on the first and second select transistor; and a second operation of applying a second voltage higher than the first voltage to the gate of the first memory cell transistor, while turning off the first and second select transistor; and the second operation is performed after the first operation.Type: GrantFiled: September 5, 2018Date of Patent: March 31, 2020Assignee: Toshiba Memory CorporationInventor: Yusuke Higashi
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Publication number: 20200091174Abstract: An example semiconductor device includes: n conductive layers including first to nth conductive layers stacked in a first direction; a first semiconductor region of a first conductive type; a second semiconductor region of a second conductive type closer to the nth conductive layer than the first semiconductor region; a semiconductor layer provided between the first semiconductor region and the second semiconductor region, extending in the first direction, penetrating the n conductive layers, and having an impurity concentration lower than a first conductive impurity concentration of the first region and a second conductive impurity concentration of the second region; n charge storage regions including first to nth charge storage regions provided between the n conductive layers and the semiconductor layer, and a control circuit that controls a voltage applied to the n conductive layers to always prevent charges from being stored in at least one of the n charge storage regions.Type: ApplicationFiled: February 22, 2019Publication date: March 19, 2020Applicant: Toshiba Memory CorporationInventors: Tomoya SANUKI, Yusuke HIGASHI, Hideto HORII, Masaki KONDO, Hiroki TOKUHIRA, Hideaki AOCHI
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Publication number: 20200066868Abstract: A semiconductor memory device of an embodiment includes a semiconductor layer; a gate electrode including a first portion, a second portion provided to be spaced apart from the first portion, and a spacer provided between the first portion and the second portion; and a first insulating layer provided between the semiconductor layer and the gate electrode and including a first region containing a ferroelectric, a ferrielectric, or an anti-ferroelectric, a second region containing a ferroelectric, a ferrielectric, or an anti-ferroelectric, and a boundary region provided between the first region and the second region. The first region is positioned between the first portion and the semiconductor layer, the second region is positioned between the second portion and the semiconductor layer, the boundary region is positioned between the spacer and the semiconductor layer, and the boundary region has a chemical composition different from that of the spacer.Type: ApplicationFiled: October 31, 2019Publication date: February 27, 2020Applicant: Toshiba Memory CorporationInventors: Tsunehiro INO, Yusuke Higashi, Toshinori Numata, Yuuichi Kamimuta
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Patent number: 10510862Abstract: A semiconductor memory device of an embodiment includes a semiconductor layer; a gate electrode including a first portion, a second portion provided to be spaced apart from the first portion, and a spacer provided between the first portion and the second portion; and a first insulating layer provided between the semiconductor layer and the gate electrode and including a first region containing a ferroelectric, a ferrielectric, or an anti-ferroelectric, a second region containing a ferroelectric, a ferrielectric, or an anti-ferroelectric, and a boundary region provided between the first region and the second region. The first region is positioned between the first portion and the semiconductor layer, the second region is positioned between the second portion and the semiconductor layer, the boundary region is positioned between the spacer and the semiconductor layer, and the boundary region has a chemical composition different from that of the spacer.Type: GrantFiled: September 18, 2018Date of Patent: December 17, 2019Assignee: Toshiba Memory CorporationInventors: Tsunehiro Ino, Yusuke Higashi, Toshinori Numata, Yuuichi Kamimuta
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Publication number: 20190296122Abstract: A semiconductor memory device of an embodiment includes a semiconductor layer; a gate electrode including a first portion, a second portion provided to be spaced apart from the first portion, and a spacer provided between the first portion and the second portion; and a first insulating layer provided between the semiconductor layer and the gate electrode and including a first region containing a ferroelectric, a ferrielectric, or an anti-ferroelectric, a second region containing a ferroelectric, a ferrielectric, or an anti-ferroelectric, and a boundary region provided between the first region and the second region. The first region is positioned between the first portion and the semiconductor layer, the second region is positioned between the second portion and the semiconductor layer, the boundary region is positioned between the spacer and the semiconductor layer, and the boundary region has a chemical composition different from that of the spacer.Type: ApplicationFiled: September 18, 2018Publication date: September 26, 2019Applicant: Toshiba Memory CorporationInventors: Tsunehiro INO, Yusuke Higashi, Toshinori Numata, Yuuichi Kamimuta
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Patent number: 10424384Abstract: A semiconductor memory device includes an n-type semiconductor region, first to fourth conductive layers above the n-type semiconductor region, a p-type semiconductor region, a semiconductor layer between the n-type semiconductor region and the p-type semiconductor region and extending through the conductive layers, charge storage regions between the conductive layers and the semiconductor layer, a control circuit that executes a first read sequence and a second read sequence following the first read sequence, a comparison circuit that compares the first data read in the first read sequence to the second data read in the second read sequence, and a determination circuit that selects one of the first data and the second data as a true read value. The first and second read sequences each have an off step and an off voltage applied during the first read sequence is different from an off voltage applied during the second read sequence.Type: GrantFiled: August 27, 2018Date of Patent: September 24, 2019Assignee: Toshiba Memory CorporationInventors: Yusuke Higashi, Tomoya Sanuki
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Publication number: 20190287599Abstract: A semiconductor memory device according to one embodiment includes: a memory cell, the memory cell including a ferroelectric film; and a control circuit controlling the memory cell. Additionally, the control circuit determining whether the number of times of executions of a write process or an erase process on the memory cell has reached a predetermined number of times; and, if the number of times of executions has reached the predetermined number of times, executing a voltage application process in which a first voltage of a first polarity and a second voltage of a second polarity opposite to the first polarity are applied to the ferroelectric film.Type: ApplicationFiled: August 27, 2018Publication date: September 19, 2019Applicant: TOSHIBA MEMORY CORPORATIONInventors: Yusuke Higashi, Yuuichi Kamimuta, Tsunehiro Ino
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Publication number: 20190267097Abstract: A semiconductor memory device includes an n-type semiconductor region, first to fourth conductive layers above the n-type semiconductor region, a p-type semiconductor region, a semiconductor layer between the n-type semiconductor region and the p-type semiconductor region and extending through the conductive layers, charge storage regions between the conductive layers and the semiconductor layer, a control circuit that executes a first read sequence and a second read sequence following the first read sequence, a comparison circuit that compares the first data read in the first read sequence to the second data read in the second read sequence, and a determination circuit that selects one of the first data and the second data as a true read value. The first and second read sequences each have an off step and an off voltage applied during the first read sequence is different from an off voltage applied during the second read sequence.Type: ApplicationFiled: August 27, 2018Publication date: August 29, 2019Inventors: Yusuke HIGASHI, Tomoya SANUKI
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Publication number: 20190198111Abstract: According to one embodiment, a semiconductor storage device includes: a first select transistor connected at a first end of a memory string; a second select transistor connected at a second end of the memory string; and a controller. In a write operation of writing data into a first memory cell transistor of the memory string, the controller performs: a first operation of applying a first voltage to a gate of the first memory cell transistor, while turning on the first and second select transistor; and a second operation of applying a second voltage higher than the first voltage to the gate of the first memory cell transistor, while turning off the first and second select transistor; and the second operation is performed after the first operation.Type: ApplicationFiled: September 5, 2018Publication date: June 27, 2019Applicant: Toshiba Memory CorporationInventor: Yusuke HIGASHI
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Publication number: 20180276557Abstract: According to one embodiment, a quantum annealing machine 1 includes a quantum bit array 21 which includes a plurality of cells (quantum bits) 211 respectively including a floating gate 105, and a controller 10 which executes writing of data in the plurality of cells 211, and temporally controls tunneling of an electric charge with respect to the floating gate 105.Type: ApplicationFiled: September 11, 2017Publication date: September 27, 2018Applicant: Toshiba Memory CorporationInventors: Tetsufumi Tanamoto, Yusuke Higashi, Takao Marukame, Shinichi Yasuda, Jun Deguchi
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Patent number: 10078550Abstract: According to an embodiment, a memory system includes a memory and a computation unit. Into the memory, data are written. The memory stores therein multiple check matrices. Each of the check matrices is associated with the number of errors in the written data. The computation unit is configured to perform a first error correction on the written data by selectively using, from among the check matrices, a check matrix associated with the number of errors recognized in the written data.Type: GrantFiled: September 1, 2015Date of Patent: September 18, 2018Assignee: Kabushiki Kaisha ToshibaInventors: Takao Marukame, Yoshifumi Nishi, Yusuke Higashi, Jiezhi Chen, Kazuya Matsuzawa, Yuichiro Mitani
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Patent number: 9924117Abstract: According to an embodiment, an imaging element includes a plurality of light receiving elements, a plurality of scanning circuits, a first line comprising a plurality of nodes, and a plurality of first variable resistance elements. The plurality of scanning circuits are respectively connected to the plurality of light receiving elements. Each of the plurality of first variable resistance elements is connected between the corresponding one of the nodes and a corresponding one of the scanning circuits. At least one of the first variable resistance elements includes a plurality of resistance elements connected to each other in parallel.Type: GrantFiled: September 8, 2015Date of Patent: March 20, 2018Assignee: Kabushiki Kaisha ToshibaInventors: Yusuke Higashi, Takao Marukame, Masamichi Suzuki, Koichiro Zaitsu, Haiyang Peng, Hiroki Noguchi, Yuichiro Mitani