Abstract: There are provided a first processor (11) to be operated at a first operating frequency, a second processor (12) in which a leakage current is reduced more greatly than the first processor and which is operated at a lower second operating frequency than the first operating frequency, and a selecting portion (10) capable of selectively switching an executing destination of an application software into the first processor and the second processor corresponding to a demand operating speed of the application software. The first processor and the second processor can execute an identical instruction set, respectively. It is possible to carry out a high speed processing corresponding to the demand operating speed of the application software and to eliminate a dead current caused by a processing at a speed exceeding the demand operating speed of the application software.

Abstract: A semiconductor integrated circuit device provided with a first circuit block BLK1, a second circuit block DRV1 and a conversion circuit MIO1 for connecting the first circuit block to the second circuit block. The first circuit block includes a first mode for applying a supply voltage and a second mode for shutting off the supply voltage. The conversion circuit is provided with a function for maintaining the potential of an input node of the second circuit block at an operation potential, thereby suppressing a penetrating current flow when the first circuit block is in the second mode. The conversion circuit (MIO1 to MIO4) are commonly used for connecting circuit blocks.

Abstract: In a low power consumption mode in which prior data is retained upon power shutdown, the return speed thereof is increased. While use of an existent data retaining flip-flop may be considered, this is not preferred since it increases area overhead such as enlargement of the size of a cell. A power line for data retention for power shutdown is formed with wirings finer than a usual main power line. Preferably, power lines for a data retention circuit are considered as signal lines and wired by automatic placing and mounting. For this purpose, terminals for the power line for data retention are previously designed by providing the terminals therefor for the cell in the same manner as in the existent signal lines. Additional layout for power lines is no longer necessary for the cell, which enables a decrease in the area and design by an existent placing and routing tool.

Abstract: To enhance the speed of first access (read access different in word line from the previous access) to a multi-bank memory, multi-bank memory macro structures are used. Data are held in a sense amplifier for every memory bank. When access is hit to the held data, data latched by the sense amplifier are output to thereby enhance the speed of first access to the memory macro structures. Namely, each memory bank is made to function as a sense amplifier cache. To enhance the hit ratio of such a sense amplifier cache more greatly, an access controller self-prefetches the next address (an address to which a predetermined offset has been added) after access to a memory macro structure so that data in the self-prefetched address are preread by a sense amplifier in another memory bank.

Abstract: A semiconductor device including a level converter (LSC) is disclosed. The level converter comprises a voltage-up circuit (LSC1) that operates on low voltage of power supply (VDD) and steps up voltage enough to drive the level converter and a level converter circuit (LSC2) that operates on high voltage of power supply (VDDQ). The voltage-up circuit is capable of constantly generating 2×VDD so that the level converter can convert a low voltage of power supply (VDD) below 1 V to VDDQ. This voltage-up circuit can be configured only with MOSFET transistors produced by thin oxide film deposition, thus enabling high-speed operation. To facilitate designing a circuit for preventing a leakage current from occurring in the level converter during sleep mode of a low-voltage-driven circuit (CB1), the level converter circuit (LSC2) includes a leak protection circuit (LPC) that exerts autonomous control for leak prevention, dispensing with external control signals.

Abstract: To enhance the speed of first access (read access different in word line from the previous access) to a multi-bank memory, multi-bank memory macro structures are used. Data are held in a sense amplifier for every memory bank. When access is hit to the held data, data latched by the sense amplifier are output to thereby enhance the speed of first access to the memory macro structures. Namely, each memory bank is made to function as a sense amplifier cache. To enhance the hit ratio of such a sense amplifier cache more greatly, an access controller self-prefetches the next address (an address to which a predetermined offset has been added) after access to a memory macro structure so that data in the self-prefetched address are preread by a sense amplifier in another memory bank.

Abstract: A low power consumption in a semiconductor integrated circuit device can be achieved by reducing a glitch power in a flip-flop. In a pulse-generator-incorporated auto-clock-gating flip-flop in which data latch is performed by using a pulsed clock, input data is latched based on an output of a dynamic XOR circuit, which is a comparator circuit, during a period when the pulsed clock is at a high level, and the dynamic XOR circuit is cut off during a period when the pulsed clock is at a low level.

Abstract: In an information processing apparatus involving a cache accessed by INDEX and TAG addresses, accesses to the main memory include many accesses attributable to the local character of referencing and write-back accesses attributable to the replacement of cache contents. Accordingly, high speed accessing requires efficient assignment of the two kinds of accesses to banks of the DRAM. In assigning request addresses from the CPU to different banks of the DRAM, bank addresses of the DRAM and generated by operation of the INDEX field and the TAG field so that local accesses whose INDEX varies and accesses at the time of writing back of which INDEX remains the same but TAG differs can be assigned to different banks. High speed accessing is made possible because accesses to the main memory can be assigned to separate banks.

Abstract: A semiconductor integrated circuit device is provided, the circuit being capable of arranging a control signal system, avoiding a danger of failure to check an indefinite signal propagation prevention circuit or the like, further facilitating a check oriented to mounting on an automated tool, and facilitating power shutdown control inside of a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains Area A to Area I. A rule is provided, the rule defining that, in the case where a circuit having a high priority is turned ON, a power domain having its lower priority cannot be turned OFF, thereby facilitating a designing method. In addition, areas capable of applying still another power supply are provided in the independent power areas Area A to Area I. In that area, a relay buffer (repeater) and a clock buffer or an information retaining latch for saving information are integrated.

Abstract: The present invention provides a sense circuit for DRAM memory cell to cover the events that a sense time becomes remarkably longer when a power source voltage is lowered, a sense time under the low voltage condition becomes shorter when temperature rises and a sense time changes to a large extent for fluctuation of processes. The present invention provides the following typical effects. A switch means is provided between the bit line BL and local bit line LBL connected to the memory cells for isolation and coupling of these bit lines. The bit line BL is precharged to the voltage of VDL/2, while the local bit line LBL is precharged to the voltage of VDL. The VDL is the maximum amplitude voltage of the bit line BL. A sense amplifier SA comprises a first circuit including a differential MOS pair having the gate connected to the bit line BL and a second circuit connected to the local bit line LBL for full amplitude amplification and for holding the data.

Abstract: A semiconductor integrated circuit device including an I/O circuitry capable of low-voltage high-speed operation at low cost is provided. In the I/O circuitry, when an I/O voltage (for example, 3.3 V) is lowered to a predetermined voltage (for example, 1.8 V), portions causing a speed deterioration are a level conversion unit and a pre-buffer unit for driving a main large-sized buffer. In view of this, a high voltage is applied to a level up converter and a pre-buffer circuit. By doing so, it is possible to achieve an I/O circuitry capable of low-voltage high-speed operation at low cost.

Abstract: A semiconductor device including a level converter (LSC) is disclosed. The level converter comprises a voltage-up circuit (LSC1) that operates on low voltage of power supply (VDD) and steps up voltage enough to drive the level converter and a level converter circuit (LSC2) that operates on high voltage of power supply (VDDQ). The voltage-up circuit is capable of constantly generating 2×VDD so that the level converter can convert a low voltage of power supply (VDD) below 1 V to VDDQ. This voltage-up circuit can be configured only with MOSFET transistors produced by thin oxide film deposition, thus enabling high-speed operation. To facilitate designing a circuit for preventing a leakage current from occurring in the level converter during sleep mode of a low-voltage-driven circuit (CB1), the level converter circuit (LSC2) includes a leak protection circuit (LPC) that exerts autonomous control for leak prevention, dispensing with external control signals.

Abstract: A semiconductor device including a level converter (LSC) is disclosed. The level converter comprises a voltage-up circuit (LSC1) that operates on low voltage of power supply (VDD) and steps up voltage enough to drive the level converter and a level converter circuit (LSC2) that operates on high voltage of power supply (VDDQ). The voltage-up circuit is capable of constantly generating 2×VDD so that the level converter can convert a low voltage of power supply (VDD) below 1 V to VDDQ. This voltage-up circuit can be configured only with MOSFET transistors produced by thin oxide film deposition, thus enabling high-speed operation. To facilitate designing a circuit for preventing a leakage current from occurring in the level converter during sleep mode of a low-voltage-driven circuit (CB1), the level converter circuit (LSC2) includes a leak protection circuit (LPC) that exerts autonomous control for leak prevention, dispensing with external control signals.

Abstract: The present invention provides a sense circuit for DRAM memory cell to cover the events that a sense time becomes remarkably longer when a power source voltage is lowered, a sense time under the low voltage condition becomes shorter when temperature rises and a sense time changes to a large extent for fluctuation of processes. The present invention provides the following typical effects. A switch means is provided between the bit line BL and local bit line LBL connected to the memory cells for isolation and coupling of these bit lines The bit line BL is precharged to the voltage of VDL/2, while the local bit line LBL is precharged to the voltage of VDL. The VDL is the maximum amplitude voltage of the bit line BL. A sense amplifier SA comprises a first circuit including a differential MOS pair having the gate connected to the bit line BL and a second circuit connected to the local bit line LBL for full amplitude amplification and for holding the data.

Abstract: In a low power consumption mode in which prior data is retained upon power shutdown, the return speed thereof is increased. While use of an existent data retaining flip-flop may be considered, this is not preferred since it increases area overhead such as enlargement of the size of a cell. A power line for data retention for power shutdown is formed with wirings finer than a usual main power line. Preferably, power lines for a data retention circuit are considered as signal lines and wired by automatic placing and mounting. For this purpose, terminals for the power line for data retention are previously designed by providing the terminals therefor for the cell in the same manner as in the existent signal lines. Additional layout for power lines is no longer necessary for the cell, which enables a decrease in the area and design by an existent placing and routing tool.

Abstract: A semiconductor integrated circuit device provided with a first circuit block BLK1, a second circuit block DRV1 and a conversion circuit MIO1 for connecting the first circuit block to the second circuit block. The first circuit block includes a first mode for applying a supply voltage and a second mode for shutting off the supply voltage. The conversion circuit is provided with a function for maintaining the potential of an input node of the second circuit block at an operation potential, thereby suppressing a penetrating current flow when the first circuit block is in the second mode. The conversion circuit (MIO1 to MIO4) are commonly used for connecting circuit blocks.

Abstract: In a low power consumption mode in which prior data is retained upon power shutdown, the return speed thereof is increased. While use of an existent data retaining flip-flop may be considered, this is not preferred since it increases area overhead such as enlargement of the size of a cell. A power line for data retention for power shutdown is formed with wirings finer than a usual main power line. Preferably, power lines for a data retention circuit are considered as signal lines and wired by automatic placing and mounting. For this purpose, terminals for the power line for data retention are previously designed by providing the terminals therefor for the cell in the same manner as in the existent signal lines. Additional layout for power lines is no longer necessary for the cell, which enables a decrease in the area and design by an existent placing and routing tool.

Abstract: The present invention provides a sense circuit for DRAM memory cell to cover the events that a sense time becomes remarkably longer when a power source voltage is lowered, a sense time under the low voltage condition becomes shorter when temperature rises and a sense time changes to a large extent for fluctuation of processes. The present invention provides the following typical effects. A switch means is provided between the bit line BL and local bit line LBL connected to the memory cells for isolation and coupling of these bit lines. The bit line BL is precharged to the voltage of VDL/2, while the local bit line LBL is precharged to the voltage of VDL. The VDL is the maximum amplitude voltage of the bit line BL. A sense amplifier SA comprises a first circuit including a differential MOS pair having the gate connected to the bit line BL and a second circuit connected to the local bit line LBL for full amplitude amplification and for holding the data.

Abstract: A semiconductor device includes a differential level converter circuit that receives a first signal and outputs a second signal of greater amplitude. The differential level converter has a first MISFET pair for receiving the first signal, a second MISFET pair for enhancing the withstand voltage of the first MISFET pair, and a third MISFET pair with cross-coupled gates for latching the second signal from output. The film thickness of the gate insulating films of the second and third MISFET pairs is made thicker than that of the first MISFET pair, and the threshold voltages of the first and second MISFET pairs are made smaller than that of the third MISFET pair. This level converter circuit operates at high speed even if there is a large difference in the signal amplitude before and after level conversion.

Abstract: A semiconductor device includes a differential level converter circuit that receives a first signal and outputs a second signal of greater amplitude. The differential level converter has a first MISFET pair for receiving the first signal, a second MISFET pair for enhancing the withstand voltage of the first MISFET pair, and a third MISFET pair with cross-coupled gates for latching the second signal from output. The film thickness of the gate insulating films of the second and third MISFET pairs is made thicker than that of the first MISFET pair, and the threshold voltages of the first and second MISFET pairs are made smaller than that of the third MISFET pair. This level converter circuit operates at high speed even if there is a large difference in the signal amplitude before and after level conversion.