Abstract: In an information processing apparatus involving a cache accessed by INDEX and TAG addresses, accesses to the main memory include many accesses attributable to the local character of referencing and write-back accesses attributable to the replacement of cache contents. Accordingly, high speed accessing requires efficient assignment of the two kinds of accesses to banks of the DRAM. In assigning request addresses from the CPU to different banks of the DRAM, bank addresses of the DRAM are generated by operation of the INDEX field and the TAG field so that local accesses whose INDEX varies and accesses at the time of writing back of which INDEX remains the same but TAG differs can be assigned to different banks, thereby enabling high speed accessing. Furthermore, as reading and writing at the time of writing back can be assigned to a separate bank, pseudo dual-port accessing is made possible with only one port, resulting in higher speed write-back accessing.

Abstract: A semiconductor integrated circuit is disclosed, in which a memory is activated at high speed in commensurate with a high-speed logic circuit mounted with the memory in order to reduce the cost using a DRAM of a 3-transistor cell requiring no capacitor. A pair of data lines connected with a plurality of memory cells having the amplification function are set to different precharge voltage values, thereby eliminating the need of a dummy cell. The elimination of the need of the dummy cell unlike in the conventional DRAM circuit using a gain cell reduces both the required space and the production cost. A hierarchical structure of the data lines makes a high-speed operation possible. Also, a DRAM circuit can be fabricated through a fabrication process matched with an ordinary logic element.

Abstract: To enhance the speed of first access (read access different in word line from the previous access) to a multi-bank memory, multi-bank memory macro structures are used. Data are held in a sense amplifier for every memory bank. When access is hit to the held data, data latched by the sense amplifier are output to thereby enhance the speed of first access to the memory macro structures. Namely, each memory bank is made to function as a sense amplifier cache. To enhance the hit ratio of such a sense amplifier cache more greatly, an access controller self-prefetches the next address (an address to which a predetermined offset has been added) after access to a memory macro structure so that data in the self-prefetched address are preread by a sense amplifier in another memory bank.

Abstract: A semiconductor device includes a differential level converter circuit that receives a first signal and outputs a second signal of greater amplitude. The differential level converter has a first MISFET pair for receiving the first signal, a second MISFET pair for enhancing the withstand voltage of the first MISFET pair, and a third MISFET pair with cross-coupled gates for latching the second signal from output. The film thickness of the gate insulating films of the second and third MISFET pairs is made thicker than that of the first MISFET pair, and the threshold voltages of the first and second MISFET pairs are made smaller than that of the third MISFET pair. This level converter circuit operates at high speed even if there is a large difference in the signal amplitude before and after level conversion.

Abstract: The present invention provides a sense circuit for DRAM memory cell to cover the events that a sense time becomes remarkably longer when a power source voltage is lowered, a sense time under the low voltage condition becomes shorter when temperature rises and a sense time changes to a large extent for fluctuation of processes. The present invention provides the following typical effects. A switch means is provided between the bit line BL and local bit line LBL connected to the memory cells for isolation and coupling of these bit lines. The bit line BL is precharged to the voltage of VDL/2, while the local bit line LBL is precharged to the voltage of VDL. The VDL is the maximum amplitude voltage of the bit line BL.

Abstract: A body bias control system allows for independent design of a functional module, thereby reducing the burden of designing the module. The body bias control system provides a switch circuit having an area in which the body bias is controlled independently of its outside portion, for controlling the supply of body bias in the vicinity of the area. Preferably three types of switches are provided for switching the body bias to suitable levels for a standby mode, a mode of normal operation and a mode of high-speed operation.

Abstract: A dynamic memory requires refreshing to retain data in its memory cells. This may cause access to the dynamic memory for purposes other than refreshing (external access) and access to it for refreshing to compete with each other, resulting in a performance deterioration. According to this invention, a pipelined dynamic memory (PDRAM) is used, and the pipeline frequency (CLK) of the pipelined dynamic memory is made higher than the frequency (CLK1) of external access, and access required for refreshing is made to an unoccupied slot (a timing when any external access request is never issued) in the pipeline of the pipelined dynamic memory. This makes refreshing of the internal dynamic memory an internal operation, which eliminates the need to take refreshing into consideration at the time external access is made, leading to improvement in operating ease and speed.

Abstract: A semiconductor integrated circuit that is well-balanced between increased operating speed and decreased power consumption caused by a leakage current. The gate cells of the circuit comprised of low threshold voltage MOSs are used for logic gates provided with three or more inputs, and gate cells comprised of high threshold voltage MOSs are generally used for logic gates provided with one or two inputs, sometimes on a case-by-case basis.

Abstract: A semiconductor integrated circuit is disclosed, in which a memory is activated at high speed in commensurate with a high-speed logic circuit mounted with the memory in order to reduce the cost using a DRAM of a 3-transistor cell requiring no capacitor. A pair of data lines connected with a plurality of memory cells having the amplification function are set to different precharge voltage values, thereby eliminating the need of a dummy cell. The elimination of the need of the dummy cell unlike in the conventional DRAM circuit using a gain cell reduces both the required space and the production cost. A hierarchical structure of the data lines makes a high-speed operation possible. Also, a DRAM circuit can be fabricated through a fabrication process matched with an ordinary logic element.

Abstract: A semiconductor integrated circuit device provided with a first circuit block BLK1, a second circuit block DRV1 and a conversion circuit MIO1 for connecting the first circuit block to the second circuit block. The first circuit block includes a first mode for applying a supply voltage and a second mode for shutting off the supply voltage. The conversion circuit is provided with a function for maintaining the potential of an input node of the second circuit block at an operation potential, thereby suppressing a penetrating current flow when the first circuit block is in the second mode. The conversion circuit (MIO1 to MIO4) are commonly used for connecting circuit blocks.

Abstract: A semiconductor integrated circuit is disclosed, in which a memory is activated at high speed in commensurate with a high-speed logic circuit mounted with the memory in order to reduce the cost using a DRAM of a 3-transistor cell requiring no capacitor. A pair of data lines connected with a plurality of memory cells having the amplification function are set to different precharge voltage values, thereby eliminating the need of a dummy cell. The elimination of the need of the dummy cell unlike in the conventional DRAM circuit using a gain cell reduces both the required space and the production cost. A hierarchical structure of the data lines makes a high-speed operation possible. Also, a DRAM circuit can be fabricated through a fabrication process matched with an ordinary logic element.

Abstract: A semiconductor device includes a differential level converter circuit that receives a first signal and outputs a second signal of greater amplitude. The differential level converter has a first MISFET pair for receiving the first signal, a second MISFET pair for enhancing the withstand voltage of the first MISFET pair, and a third MISFET pair with cross-coupled gates for latching the second signal from output. The film thickness of the gate insulating films of the second and third MISFET pairs is made thicker than that of the first MISFET pair, and the threshold voltages of the first and second MISFET pairs are made smaller than that of the third MISFET pair. This level converter circuit operates at high speed even if there is a large difference in the signal amplitude before and after level conversion.

Abstract: To provide means that can hide refresh operations even when the data width of a cache line differs from that of the external data bus in a memory that uses a cache memory and a DRAM consisting of a plurality of banks.

Abstract: A semiconductor integrated circuit is disclosed, in which a memory is activated at high speed in commensurate with a high-speed logic circuit mounted with the memory in order to reduce the cost using a DRAM of a 3-transistor cell requiring no capacitor. A pair of data lines connected with a plurality of memory cells having the amplification function are set to different precharge voltage values, thereby eliminating the need of a dummy cell. The elimination of the need of the dummy cell unlike in the conventional DRAM circuit using a gain cell reduces both the required space and the production cost. A hierarchical structure of the data lines makes a high-speed operation possible. Also, a DRAM circuit can be fabricated through a fabrication process matched with an ordinary logic element.

Abstract: A semiconductor integrated circuit that is well-balanced between increased operating speed and decreased power consumption caused by a leakage current. The gate cells of the circuit comprised of low threshold voltage MOSs are used for logic gates provided with three or more inputs, and gate cells comprised of high threshold voltage MOSs are generally used for logic gates provided with one or two inputs, sometimes on a case-by-case basis.

Abstract: A dynamic memory requires refreshing to retain data in its memory cells. This may cause access to the dynamic memory for purposes other than refreshing (external access) and access to it for refreshing to compete with each other, resulting in a performance deterioration According to this invention, a pipelined dynamic memory (PDRAM) is used, and the pipeline frequency (CLK) of the pipelined dynamic memory is made higher than the frequency (CLK1) of external access, and access required for refreshing is made to an unoccupied slot (a timing when any external access request is never issued) in the pipeline of the pipelined dynamic memory This makes refreshing of the internal dynamic memory an internal operation, which eliminates the need to take refreshing into consideration at the time external access is made, leading to improvement in operating ease and speed.

Abstract: A semiconductor device including a level converter (LSC) is disclosed. The level converter comprises a voltage-up circuit (LSC1) that operates on low voltage of power supply (VDD) and steps up voltage enough to drive the level converter and a level converter circuit (LSC2) that operates on high voltage of power supply (VDDQ). The voltage-up circuit is capable of constantly generating 2×VDD so that the level converter can convert a low voltage of power supply (VDD) below 1 V to VDDQ. This voltage-up circuit can be configured only with MOSFET transistors produced by thin oxide film deposition, thus enabling high-speed operation. To facilitate designing a circuit for preventing a leakage current from occurring in the level converter during sleep mode of a low-voltage-driven circuit (CB1), the level converter circuit (LSC2) includes a leak protection circuit (LPC) that exerts autonomous control for leak prevention, dispensing with external control signals.

Abstract: In an information processing apparatus involving a cache accessed by INDEX and TAG addresses, accesses to the main memory include many accesses attributable to the local character of referencing and write-back accesses attributable to the replacement of cache contents. Accordingly, high speed accessing requires efficient assignment of the two kinds of accesses to banks of the DRAM.

Abstract: A dynamic memory requires refreshing to retain data in its memory cells. This may cause access to the dynamic memory for purposes other than refreshing (external access) and access to it for refreshing to compete with each other, resulting in a performance deterioration. According to this invention, a pipelined dynamic memory. (PDRAM) is used, and the pipeline frequency (CLK) of the pipelined dynamic memory is made higher than the frequency (CLK1) of external access, and access required for refreshing is made to an unoccupied slot (a timing when any external access request is never issued) in the pipeline of the pipelined dynamic memory. This makes refreshing of the internal dynamic memory an internal operation, which eliminates the need to take refreshing into consideration at the time external access is made, leading to improvement in operating ease and speed.

Abstract: In an information processing apparatus involving a cache accessed by INDEX and TAG addresses, accesses to the main memory include many accesses attributable to the local character of referencing and write-back accesses attributable to the replacement of cache contents. Accordingly, high speed accessing requires efficient assignment of the two kinds of accesses to banks of the DRAM. In assigning request addresses from the CPU to different banks of the DRAM, bank addresses of the DRAM and generated by operation of the INDEX field and the TAG field so that local accesses whose INDEX varies and accesses at the time of writing back of which INDEX remains the same but TAG differs can be assigned to different banks. High speed accessing is made possible because accesses to the main memory can be assigned to separate banks.