Abstract: In a method of fabricating a COB DRAM cell, a polysilicon plug is formed on the source and drain in self-alignment with the gate electrode. A bit line contact and a storage electrode contact are formed on the polysilicon plug thereby to reduce the aspect ratio of both the bit line contact and the storage electrode contact. With the polysilicon plug formed in self-alignment with the gate electrode, short-circuiting of contacts of adjacent element regions and short-circuiting of the plugs of the source and drain will not occur, leading to high protection against misregistration. Moreover, an independent lithography process is not required for forming the polysilicon plug, and, therefore, the number of fabrication steps is reduced.

Abstract: A semiconductor device includes a first N-type region formed in a P-type silicon substrate, trenches formed in the substrate, second N-type regions each formed from at least the bottom of a corresponding one of the trenches into the substrate, these second N-type regions contacting each other to constitute a wiring layer and being also in contact with the first N-type region, and an electrode for applying a predetermined potential to the second N-type regions via the first N-type region. Since a potential is supplied to the wiring layer formed in the substrate via the first N-type region, no special design, such as formation of a terminal trench, is required. A potential can be easily supplied to the wiring layer formed in the semiconductor substrate, and the device can be easily fabricated.

Abstract: Trenches are formed in a silicon oxide film, a barrier metal film and tungsten film are formed, and the surface portion is polished to make the surface flat and form interconnection layers of the tungsten film in the trenches. Then, the tungsten film and barrier film are etched to form a stepped portions, a silicon nitride film is formed to fill the stepped portions, and the silicon nitride film is polished to make the surface flat. After this, the silicon oxide film is etched by use of a mask pattern to form contact holes in a self-aligned manner. Then, a silicon nitride film is formed and the surface portions is etched back to form side walls on the side walls of the contact holes and a barrier metal film and tungsten film are sequentially formed to fill the contact holes, then the tungsten film and barrier metal film are polished until the silicon oxide film and silicon nitride film are exposed, and as a result, the surface is made flat.

Abstract: A mask for exposure includes a light transmitting substrate, a plurality of substantially oblong, island-like light transmitting sections arranged periodically on the substrate, an opaque section formed on the substrate except where the light transmitting sections are arranged, and a plurality of phase shifter layers selectively formed in the light transmitting sections. The light transmitting sections include paired light transmitting sections opposed to each other at one end portion, and one of the phase shifter layers is formed in one of the paired light transmitting sections. An interval between the paired light transmitting sections at one end portion is smaller than an interval between adjacent ones of the light transmitting sections at portions other than the one end portion.

Abstract: A DRAM cell includes first and second trenches formed in a P-type silicon substrate, a first N-type diffusion layer formed around the first trench, and a second N-type diffusion layer formed around the second trench, contacting the first N-type diffusion layer, and reaching the surface of the substrate. In the first trench, a storage node electrode whose capacitance is coupled to the first N-type diffusion layer and a conductive polysilicon film for leading the storage node electrode to the surface of the substrate are provided. One of source and drain regions of each cell transistor is connected to the conductive polysilicon film. The first N-type diffusion layer is connected to the second N-type diffusion layer, and the second diffusion layer is connected to a plate potential supply-line.

Abstract: A semiconductor device includes a first N-type region formed in a P-type silicon substrate, trenches formed in the substrate, second N-type regions each formed from at least the bottom of a corresponding one of the trenches into the substrate, these second N-type regions contacting each other to constitute a wiring layer and being also in contact with the first N-type region, and an electrode for applying a predetermined potential to the second N-type regions via the first N-type region. Since a potential is supplied to the wiring layer formed in the substrate via the first N-type region, no special design, such as formation of a terminal trench, is required. A potential can be easily supplied to the wiring layer formed in the semiconductor substrate, and the device can be easily fabricated.

Abstract: An insulation film is interposed between a first-level wiring layer and a second-level wiring layer. A contact hole is formed in the insulation film on the first-level wiring layer to electrically connect the first-level wiring layer and second-level wiring layer. The contact hole is larger than the width of the first-level wiring layer and second-level wiring layer. The second-level wiring layer is formed on a side wall and a bottom portion of the contact hole and electrically connected to the first-level wiring layer.

Abstract: In formation of a DRAM, a silicon nitride film is used as a mask to simultaneously expose a semiconductor substrate serving as an active region where an MOSFET is formed and a portion of the periphery of a trench. Therefore, even if the alignment offset of a resist pattern occurs, an interval between adjacent memory cells does not change. The interval between the adjacent memory cells is constantly the same as that when no alignment offset of the resist patter occurs. That is, only an n-type diffusion layer of the memory cell formed at a position adjacent to the trench comes close to source and drain regions of the adjacent memory cell.

Abstract: The present structure is characterized by the electrode of a trench capacitor of a DRAM and a periphery thereof. A trench is formed adjacent to an N type region in a substrate. An insulating film is formed on the side wall of this trench and only a part of the insulating film around the upper portion of the trench is removed, forming a window. An N type polycrystalline silicon film of a lower capacitor electrode is formed over a region from the bottom of the trench to below the window, and a capacitor insulating film is formed on this polycrystalline silicon film. A polycrystalline silicon film which becomes a first upper capacitor electrode is formed on the capacitor insulating film, filling the trench up to the lower edge of the window. A monocrystalline silicon film which becomes a second upper capacitor electrode is formed on the latter polycrystalline silicon film in such a way as to contact an N type region, filling the upper portion of the trench.

Abstract: A first contact hole for a bit line is formed in an interlayer insulating film, and a polysilicon film is formed on the inner surface of the contact hole and on the interlayer insulating film. Subsequently, the polysilicon film is subjected to isotropic dry etching using a resist as a mask, and the interlayer insulating film is subjected to RIE etching, thereby forming a second contact hole in the interlayer insulating film in a peripheral circuit region. Then, a laminated film is formed on the inner surface of the second contact hole and on the polysilicon film, and the second contact hole is filled with a filling member. The laminated film and the polysilicon film are patterned, thereby forming a bit line in a memory cell region.

Abstract: This invention discloses a semiconductor device comprising a semiconductor substrate, a first conducting layer formed on the surface of the semiconductor substrate, an insulating layer formed above the semiconductor substrate, the insulating layer having a contact hole reaching the first conducting layer to expose it, a second conducting layer formed on the insulating layer, the sidewall of the contact hole, and the first conducting layer, and an anti-oxidation layer formed on at least part of the surface of the second conducting layer.

Abstract: The first element separation oxide film consisting of a plurality of line-shaped portions parallel to the bit line is formed on the surface of the P-type silicon substrate. The first and second trenches are formed in that portion of the P-type silicon substrate which is located between an adjacent pair of line-shaped portions of the first element separation oxide film such that both sides of the trenches come in contact with the first element separation oxide film. A sheath plate capacitor is formed in each of the trenches. The second element separation oxide film having a thickness less than that of the first element separation oxide film is formed on that portion of the surface of the P-type silicon substrate which is located between the first and second trenches.

Abstract: After a trench is formed in a semiconductor substrate, a semiconductor film is formed on the inner wall of the trench. Annealing is performed in a predetermined condition to subject an unwanted metal impurity to gettering into the semiconductor film. The semiconductor film is then oxidized.

Abstract: In formation of a DRAM, a silicon nitride film is used as a mask to simultaneously expose a semiconductor substrate serving as an active region where an MOSFET is formed and a portion of the periphery of a trench. Therefore, even if the alignment offset of a resist pattern occurs, an interval between adjacent memory cells does not change. The interval between the adjacent memory cells is constantly the same as that when no alignment offset of the resist patter occurs. That is, only an n-type diffusion layer of the memory cell formed at a position adjacent to the trench comes close to source and drain regions of the adjacent memory cell.

Abstract: A semiconductor device comprises a first insulating layer, a gate electrode formed on the insulating layer, a second insulating layer formed on the gate electrode, an opening formed through the second insulating layer, the gate electrode and the first insulating layer, a gate insulating layer formed to overlay the inner surface of the opening, a monocrystalline silicon layer formed on the gate insulating layer within the opening to oppose the gate electrode, a monocrystalline silicon layer formed within the opening to make contact with the monocrystalline silicon layer and oppose the first insulating layer, and a monocrystalline silicon layer formed within the opening to make contact with the monocrystalline silicon layer and oppose the second insulating layer.

Abstract: For providing a semiconductor memory device that includes a plurality of cross-point memory cells each having a fine device structure and a high capacitance, a bit line is formed on an insulating substrate, and a word line is disposed above the substrate so as to cross the bit line. A MOS transistor with a vertical structure, whose gate electrode is used as the word line, is provided on the bit line. A MIM (Metal-Insulator-Metal) capacitor is provided on the MOS transistor.

Abstract: According to this present invention, a semiconductor device includes source and drain diffusion layers, and a gate electrode formed on a substrate between the source diffusion layer and the drain diffusion layer. In addition, antioxidant films are respectively formed on the source diffusion layer and the drain diffusion layer. These antioxidant films are used for controlling a diffusion rate of an impurity contained in the source diffusion layer and the drain diffusion layer.

Abstract: In a stacked capacitor cell structure of a semiconductor memory device, the MIM (metal-insulator-metal) capacitor to be used as a transfer gate comprises at least a unit stack of a first insulation film, a lower capacitor electrode, a capacitor gate insulation film, an upper capacitor electrode, another capacitor gate insulation film and an extension of the lower capacitor electrode. Thus, the surface area of the lower capacitor electrode can be enlarged without increasing the plane area exclusively occupied by memory cells. Moreover, with such a configuration, since the surface area of the lower capacitor electrode can be augmented without increasing the film thickness of the electrode, the technical difficulties that the currently known methods of manufacturing semiconductor memory devices with a stacked capacitor cell structure encounter are effectively eliminated and consequently troubles such as short-circuited lower capacitor electrodes become non-existent.

Abstract: A method of manufacturing a semiconductor device comprises the steps of selectively etching a semiconductor substrate to form a groove therein, forming a first layer of a conductivity type on the sides and the bottom of the groove, forming a second layer of an insulation type along the inner surface of the first layer and the semiconductor substrate, forming a third layer of a conductivity type along the inner surface of the second layer, patterning the third layer to form a capacitor electrode, forming a fourth layer of an insulation type which covers the capacitor electrode, forming a fifth layer on the fourth layer so as to fill up the groove, etching the fifth layer so as to remain only in the groove, and forming a sixth layer of an insulation type on the fifth layer.