Abstract: A first concave portion for the element isolation, a second concave portion for an aligning mark, and a third concave portion for an anti-fuse portion are formed simultaneously within a silicon substrate. After a silicon oxide film is formed on the entire surface, the silicon oxide film positioned within the second and third concave portions is removed. Then, a gate insulating film is formed on the entire surface, followed by forming a polysilicon film on the gate insulating film. Further, these polysilicon film and gate insulating film are selectively removed to form a gate electrode above an element region, an aligning mark portion in the second concave portion, and a gate electrode for an anti-fuse portion on the bottom surface of the third concave portion.

Abstract: Semiconductor device structures, and methods for making such structures, are described that provide for fully-doped transistor source/drain regions while reducing or even avoiding boron penetration into the transistor channel, thereby improving the performance of the transistor. In addition, such a transistor may benefit from an SiGe layer that applies compressive stress to the transistor channel, thereby further improving the performance of the transistor.

Abstract: A boron ion stream may be used to implant ions, such as boron ions, into the sidewalls of an active area, such as an NFET active area. The boron ion stream has both vertical tilt and horizontal rotation components relative to the sidewalls and/or the silicon device, to provide a better line of sight onto the sidewalls. This may allow components of the silicon device to be moved closer together without unduly reducing the effectiveness of boron doping of NFET active area sidewalls, and provides an improved line of sight of a boron ion stream onto the sidewalls of an NFET active area prior to filling the surrounding trench with STI material.

Abstract: An isolated semiconductor device and method for producing the isolated semiconductor device in which the device includes a silicon-on-insulator (SOI) device formed on a substrate. A dielectric film is formed on the insulator and covers the SOI device. The dielectric film may be a single film or a multilayer film. The silicon layer of the SOI device may include a channel region and source/drain regions. The SOI device may further include a gate insulator disposed on the channel region of the silicon layer, a gate disposed on the gate insulator and sidewall spacers formed a side surface of the gate. The dielectric film may also be disposed on an edge portion of the silicon layer. The device structure may further include metallization lines connecting through the isolation dielectric to the gate and to the source/drain regions.

Abstract: Methods and apparatus are described that reduce the possibility that unintended subway short-circuits will occur between contacts of different potentials along the boundary between tensile and compressive liners (the T-C boundary). This may be done without unduly increasing the size of the semiconductor device, or even increasing the size at all over previous designs. For example, simply by adjusting the layout of the device, the contacts of two different common gates may be offset in opposing directions relative to the T-C boundary. Or, by forming a T-C boundary having a zigzag or other similar pattern, the contacts may be arranged even closer together while still reducing the likelihood of short-circuiting subways forming. Such layout adjustments do not otherwise require any additional steps or cost.

Abstract: The present invention provides a solid-state image pickup device including an image pickup pixel section which is provided on a semiconductor substrate and in which a plurality of pixels each having a photoelectric conversion element and a field-effect transistor are arranged, and a peripheral circuit section for the image pickup pixel section. An interconnect layer driving the field-effect transistor in the image pickup pixel section is formed on a first surface side of the semiconductor substrate. A light receiving surface of the photoelectric conversion element is located on a second surface side of the semiconductor substrate. The solid-state image pickup device includes a first terminal exposed from the second surface side of the semiconductor substrate, and a second terminal electrically connected to the first terminal and connectable to an external device on the first surface side of the semiconductor substrate.

Abstract: A first concave portion for the element isolation, a second concave portion for an aligning mark, and a third concave portion for an anti-fuse portion are formed simultaneously within a silicon substrate. After a silicon oxide film is formed on the entire surface, the silicon oxide film positioned within the second and third concave portions is removed. Then, a gate insulating film is formed on the entire surface, followed by forming a polysilicon film on the gate insulating film. Further, these polysilicon film and gate insulating film are selectively removed to form a gate electrode above an element region, an aligning mark portion in the second concave portion, and a gate electrode for an anti-fuse portion on the bottom surface of the third concave portion.

Abstract: An isolated semiconductor device and method for producing the isolated semiconductor device in which the device includes a silicon-on-insulator (SOI) device formed on a substrate. A dielectric film is formed on the insulator and covers the SOI device. The dielectric film may be a single film or a multilayer film. The silicon layer of the SOI device may include a channel region and source/drain regions. The SOI device may further include a gate insulator disposed on the channel region of the silicon layer, a gate disposed on the gate insulator and sidewall spacers formed a side surface of the gate. The dielectric film may also be disposed on an edge portion of the silicon layer. The device structure may further include metallization lines connecting through the isolation dielectric to the gate and to the source/drain regions.

Abstract: In a semiconductor device, a wiring pattern groove is formed in a surface portion of a silicon oxide film provided above a semiconductor substrate. A wiring layer is buried into the wiring pattern groove with a barrier metal film interposed therebetween. The barrier metal film is selectively removed from each sidewall portion of the wiring pattern groove. In other words, the barrier metal film is left only on the bottom of the wiring pattern groove. Thus, a damascene wiring layer having a hollow section whose dielectric constant is low between each sidewall of the wiring pattern groove and each side of the wiring layer can be formed in the semiconductor device.

Abstract: An isolated semiconductor device and method for producing the isolated semiconductor device in which the device includes a silicon-on-insulator (SOI) device formed on a substrate. A dielectric film is formed on the insulator and covers the SOI device. The dielectric film may be a single film or a multilayer film. The silicon layer of the SOI device may include a channel region and source/drain regions. The SOI device may further include a gate insulator disposed on the channel region of the silicon layer, a gate disposed on the gate insulator and sidewall spacers formed a side surface of the gate. The dielectric film may also be disposed on an edge portion of the silicon layer. The device structure may further include metallization lines connecting through the isolation dielectric to the gate and to the source/drain regions.

Abstract: Improved ways of controlling the boundaries between the compressive and tensile portions of a dual-stress liner in a semiconductor device are described. The boundaries may be appropriately designed to be located by a predetermined distance as measured from a PFET feature, such as the channel or the active area boundary, as opposed to being dictated by the N-well boundaries. This may provide the opportunity to improve and/or match PFET performance. By appropriately designing the boundaries between the compressive and tensile portions of the dual-stress liner, the compressive stress on a PFET may be reduced in the y direction while maintained or even increased in the x direction, potentially resulting in improved PFET performance.

Abstract: First and second wirings are formed on a first insulating film. Each of the wirings is arranged so that a conductive film, a silicon oxide film and a silicon nitride film are laminated. Thereafter, a silicon oxide insulating film is formed on the whole surface. The silicon oxide insulating film is etched so that a contact hole is formed between the first and second wirings. Since the silicon oxide film and the silicon nitride film exist on the conductive film of each wiring, the conductive film is not exposed at the time of etching. Thereafter, an insulating film is formed on a side wall of the contact hole, and the conductive film exposed through the contact hole is covered by the insulating film.

Abstract: A boron ion stream may be used to implant ions, such as boron ions, into the sidewalls of an active area, such as an NFET active area. The boron ion stream has both vertical tilt and horizontal rotation components relative to the sidewalls and/or the silicon device, to provide a better line of sight onto the sidewalls. This may allow components of the silicon device to be moved closer together without unduly reducing the effectiveness of boron doping of NFET active area sidewalls, and provides an improved line of sight of a boron ion stream onto the sidewalls of an NFET active area prior to filling the surrounding trench with STI material.

Abstract: Methods and apparatus are described that reduce the possibility that unintended subway short-circuits will occur between contacts of different potentials along the boundary between tensile and compressive liners (the T-C boundary). This may be done without unduly increasing the size of the semiconductor device, or even increasing the size at all over previous designs. For example, simply by adjusting the layout of the device, the contacts of two different common gates may be offset in opposing directions relative to the T-C boundary. Or, by forming a T-C boundary having a zigzag or other similar pattern, the contacts may be arranged even closer together while still reducing the likelihood of short-circuiting subways forming. Such layout adjustments do not otherwise require any additional steps or cost.

Abstract: In a semiconductor device, a wiring pattern groove is formed in a surface portion of a silicon oxide film provided above a semiconductor substrate. A wiring layer is buried into the wiring pattern groove with a barrier metal film interposed therebetween. The barrier metal film is selectively removed from each sidewall portion of the wiring pattern groove. In other words, the barrier metal film is left only on the bottom of the wiring pattern groove. Thus, a damascene wiring layer having a hollow section whose dielectric constant is low between each sidewall of the wiring pattern groove and each side of the wiring layer can be formed in the semiconductor device.

Abstract: Semiconductor device structures, and methods for making such structures, are described that provide for fully-doped transistor source/drain regions while reducing or even avoiding boron penetration into the transistor channel, thereby improving the performance of the transistor.

Abstract: A device, and method for manufacturing the same, including a PFET having an embedded SiGe layer where a shallow portion of the SiGe layer is closer to the PFET channel and a deep portion of the SiGe layer is further from the PFET channel. Thus, the SiGe layer has a boundary on the side facing toward the channel that is tapered. Such a configuration may allow the PFET channel to be compressively stressed by a large amount without necessarily substantially degrading extension junction characteristics. The tapered SiGe boundary may be configured as a plurality of discrete steps. For example, two, three, or more discrete steps may be formed.

Abstract: A hollow region is formed in a silicon substrate. A plurality of openings formed in the silicon layer on the hollow region is filled with a buried film. The bottom portion of the hollow region is formed with a plurality of silicon pillars, which support the silicon layer.

Abstract: First and second wirings are formed on a first insulating film. Each of the wirings is arranged so that a conductive film, a silicon oxide film and a silicon nitride film are laminated. Thereafter, a silicon oxide insulating film is formed on the whole surface. The silicon oxide insulating film is etched so that a contact hole is formed between the first and second wirings. Since the silicon oxide film and the silicon nitride film exist on the conductive film of each wiring, the conductive film is not exposed at the time of etching. Thereafter, an insulating film is formed on a side wall of the contact hole, and the conductive film exposed through the contact hole is covered by the insulating film.

Abstract: A gate insulation film is formed on a semiconductor substrate, gate electrodes are formed on the gate insulation film, and source/drain diffusion layers are formed. A silicon nitride films is formed on a side wall of the gate electrodes, a silicon oxide film is formed on the overall surface, and the silicon oxide film is etched back to have the same height as that of the gate electrodes so that the surface is flattened, and then the surface of the gate electrodes are etched by a predetermined thickness to form a first stepped portion from the silicon oxide film, the first stepped portion is filled up by a tungsten film, the surface of the tungsten film is etched by a predetermined thick ness so that a second stepped portion is formed, and then the second stepped portion is filled by a silicon nitride films.