Patents by Inventor Yusuke Matsunaga

Yusuke Matsunaga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240134039
    Abstract: A vehicle object detection system for detecting a target object in a detection area located behind and/or lateral of a subject vehicle, that is configured to generate a judgement on whether a target object which has been detected in the detection area is an alert object, to output the judgement to warning means which is configured to output a warning to a driver of the subject vehicle based on the judgement indicating that the target object is an alert object, and to generate the judgement based on: one or more positions of one or more other objects other than the target object being detected to be located between the target object and the subject vehicle, and a time period during which the target object is detected, being smaller than a specified period of time.
    Type: Application
    Filed: October 5, 2023
    Publication date: April 25, 2024
    Applicants: Continental Autonomous Mobility Germany GmbH, Toyota Jidosha Kabushiki Kaisha
    Inventors: Shoichi SEKIGUCHI, Yusuke Ishimatsu, Takashi Unigame, Issei Matsunaga
  • Publication number: 20240135823
    Abstract: A vehicle object detection system configured to generate a judgement on whether a target object which has been detected in the detection area is an alert object, and to output the judgement to a warning which is configured to output a warning to a driver of the subject vehicle based on the judgement indicating that the target object is an alert object, wherein system is configured to generate the judgement based on at least one of a comparison of a difference between a relative speed of the target object with respect to the subject vehicle and an absolute speed of the target object in a transverse direction of the subject vehicle with a specified range, and a comparison of an estimated arrival position of the target object, which is a position the target object is estimated to reach in the detection area in a specific period of time.
    Type: Application
    Filed: October 9, 2023
    Publication date: April 25, 2024
    Applicants: Continental Autonomous Mobility Germany GmbH, TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Shoichi Sekiguchi, Yusuke Ishimatsu, Takashi Unigame, Issei Matsunaga
  • Publication number: 20240097152
    Abstract: In an electrochemical device of an embodiment, a cell stack has a spacer disposed to be arranged next to an insulating sealing member in a direction orthogonal to a stack direction. A plurality of the spacers are arranged in the stack direction between a pair of end plates, and the spacer is interposed between a pair of separators adjacently arranged in the stack direction. The spacer is formed of a material whose thickness reduction ratio when an operation of the electrochemical device is executed is smaller than that of the insulating sealing member. Before the execution of the operation of the electrochemical device, the thickness of the spacer is thinner than the thickness of the insulating sealing member. Further, the thickness of the spacer keeps a state of being equal to or less than the thickness of the insulating sealing member when the operation of the electrochemical device is executed.
    Type: Application
    Filed: June 9, 2023
    Publication date: March 21, 2024
    Applicant: TOSHIBA ENERGY SYSTEMS & SOLUTIONS CORPORATION
    Inventors: Riko INUZUKA, Norikazu OSADA, Kentaro MATSUNAGA, Masahiro ASAYAMA, Shohei KOBAYASHI, Yusuke SUZUKI, Tsuneji KAMEDA
  • Patent number: 11931202
    Abstract: An ultrasound automatic scanning system according to an embodiment includes an ultrasound probe, a mechanical mechanism, and processing circuitry. The ultrasound probe transmits and receives ultrasonic wave. The mechanical mechanism holds and moves the ultrasound probe while an ultrasonic-wave transmission-reception surface of the ultrasound probe is pointed to a subject. The processing circuitry acquires a distance between a body surface of the subject and the ultrasonic-wave transmission-reception surface of the ultrasound probe based on reflected wave data collected while the ultrasound probe is moved by the mechanical mechanism. The processing circuitry generates, based on information of the distance, locus information of movement of the ultrasound probe when ultrasound scanning is executed on the subject. The mechanical mechanism executes ultrasound scanning on the subject by moving the ultrasound probe based on the locus information generated by the processing circuitry.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: March 19, 2024
    Assignee: CANON MEDICAL SYSTEMS CORPORATION
    Inventors: Yusuke Kobayashi, Satoshi Matsunaga
  • Patent number: 10520549
    Abstract: A semiconductor device includes a system bus, a plurality of Central Processing Unit (CPU) cores each connected to the system bus, including a scan chain, and being assigned one or more tasks and configured to perform one of the tasks in a normal operation state, and a diagnostic test circuit connected to the system bus and capable of communicating with the plurality of the CPU cores, and configured to perform a scan test for the plurality of the CPU cores by using the scan chain. The plurality of the CPU cores outputs a test start instruction signal to the diagnostic test circuit, when the test start instruction signal is output from one of the plurality of the CPU cores, the diagnostic test circuit performs a scan test for the one of the plurality of the CPU cores in accordance with the test start instruction signal.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: December 31, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yukitoshi Tsuboi, Hideo Nagano, Hiroshi Nagaoka, Yusuke Matsunaga, Yutaka Igaku, Naotaka Kubota
  • Publication number: 20180080984
    Abstract: A semiconductor device includes a system bus, a plurality of Central Processing Unit (CPU) cores each connected to the system bus, including a scan chain, and being assigned one or more tasks and configured to perform one of the tasks in a normal operation state, and a diagnostic test circuit connected to the system bus and capable of communicating with the plurality of the CPU cores, and configured to perform a scan test for the plurality of the CPU cores by using the scan chain. The plurality of the CPU cores outputs a test start instruction signal to the diagnostic test circuit, when the test start instruction signal is output from one of the plurality of the CPU cores, the diagnostic test circuit performs a scan test for the one of the plurality of the CPU cores in accordance with the test start instruction signal.
    Type: Application
    Filed: November 1, 2017
    Publication date: March 22, 2018
    Inventors: Yukitoshi TSUBOI, Hideo NAGANO, Hiroshi NAGAOKA, Yusuke MATSUNAGA, Yutaka IGAKU, Naotaka KUBOTA
  • Patent number: 9810738
    Abstract: Deterioration in operation performance due to a fault diagnosis is prevented. A semiconductor device 90 according to the present invention includes a plurality of CPU cores 91 to 94 each including a scan chain, and a diagnostic test circuit 95 that performs a scan test for the plurality of CPU cores 91 to 94 by using the scan chain of the CPU core. The diagnostic test circuit 95 performs a scan test for each of the plurality of CPU cores 91 to 94 in a predetermined order on a periodic basis so that execution time periods of the scan tests do not overlap each other.
    Type: Grant
    Filed: April 1, 2015
    Date of Patent: November 7, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Yukitoshi Tsuboi, Hideo Nagano, Hiroshi Nagaoka, Yusuke Matsunaga, Yutaka Igaku, Naotaka Kubota
  • Publication number: 20150293173
    Abstract: Deterioration in operation performance due to a fault diagnosis is prevented. A semiconductor device 90 according to the present invention includes a plurality of CPU cores 91 to 94 each including a scan chain, and a diagnostic test circuit 95 that performs a scan test for the plurality of CPU cores 91 to 94 by using the scan chain of the CPU core. The diagnostic test circuit 95 performs a scan test for each of the plurality of CPU cores 91 to 94 in a predetermined order on a periodic basis so that execution time periods of the scan tests do not overlap each other.
    Type: Application
    Filed: April 1, 2015
    Publication date: October 15, 2015
    Inventors: Yukitoshi TSUBOI, Hideo NAGANO, Hiroshi NAGAOKA, Yusuke MATSUNAGA, Yutaka IGAKU, Naotaka KUBOTA
  • Patent number: 7490271
    Abstract: A trace chip monitors a signal between a target logic chip having a data processing circuit mounted thereon and a memory chip having a memory storing data to be used by the target logic chip mounted therein, and traces an operation of the target logic chip. As the trace chip is implemented by a chip separate from the target logic chip and a memory chip, a debugging circuit need not be added to mass-produced articles when the trace chip is not mounted to the mass-produced articles. Thus, manufacturing cost of the articles can be reduced.
    Type: Grant
    Filed: July 27, 2006
    Date of Patent: February 10, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Motoki Higashida, Yusuke Matsunaga
  • Patent number: 7260893
    Abstract: A secondary heat exchanger subassembly, such as a transmission oil cooler, is disposed in a metal tank of a radiator and has a pair of metal fluid fittings. Either a connector ring engages a fitting extending through the opening in the tank or a connector nut extends into the opening to threadedly engage the fitting whereby the metal fittings are held to the metal tank and inserted into a furnace for being brazed into sealed relationship with the metal tank.
    Type: Grant
    Filed: January 9, 2004
    Date of Patent: August 28, 2007
    Assignee: Delphi Technologies, Inc.
    Inventors: Chris A. Calhoun, Terry Joseph Hunt, David A. Southwick, Karl Paul Kroetsch, Krzysztof Wawrocki, Khalid El Moutamid, Yusuke Matsunaga, Laurent Art
  • Patent number: 7147040
    Abstract: A heat exchanger is disclosed. A plurality of guides are integrally formed with the walls of a header tank and are used to position an oil cooler inside the tank to align a pair of fittings carried by the cooler with a pair of spaced openings in the tank.
    Type: Grant
    Filed: January 8, 2004
    Date of Patent: December 12, 2006
    Assignee: Delphi Technologies, Inc.
    Inventors: Chris A. Calhoun, Terry Joseph Hunt, David A. Southwick, Karl Paul Kroetsch, Krzysztof Wawrocki, Khalid El Moutamid, Yusuke Matsunaga, Laurent Art
  • Patent number: 7146543
    Abstract: A trace chip monitors a signal between a target logic chip having a data processing circuit mounted thereon and a memory chip having a memory storing data to be used by the target logic chip mounted therein, and traces an operation of the target logic chip. As the trace chip is implemented by a chip separate from the target logic chip and a memory chip, a debugging circuit need not be added to mass-produced articles when the trace chip is not mounted to the mass-produced articles. Thus, manufacturing cost of the articles can be reduced.
    Type: Grant
    Filed: March 11, 2003
    Date of Patent: December 5, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Motoki Higashida, Yusuke Matsunaga
  • Publication number: 20060271828
    Abstract: A trace chip monitors a signal between a target logic chip having a data processing circuit mounted thereon and a memory chip having a memory storing data to be used by the target logic chip mounted therein, and traces an operation of the target logic chip. As the trace chip is implemented by a chip separate from the target logic chip and a memory chip, a debugging circuit need not be added to mass-produced articles when the trace chip is not mounted to the mass-produced articles. Thus, manufacturing cost of the articles can be reduced.
    Type: Application
    Filed: July 27, 2006
    Publication date: November 30, 2006
    Inventors: Motoki Higashida, Yusuke Matsunaga
  • Patent number: 7059050
    Abstract: A metal tank cap is integral with a reinforcing member via a narrow connection and is flared outwardly at the narrow connection portion to be over an open end of the tank simultaneously with moving the metal tubes of the core into the tank. By unbending the connection portion, the respective tank caps are deflared into the open ends of the respective tanks and the entire assembly is placed in a furnace and brazed together.
    Type: Grant
    Filed: January 8, 2004
    Date of Patent: June 13, 2006
    Assignee: Delphi Technologies, Inc.
    Inventors: Chris A. Calhoun, Terry Joseph Hunt, David A. Southwick, Karl Paul Kroetsch, Krzysztof Wawrocki, Khalid El Moutamid, Yusuke Matsunaga, Laurent Art
  • Patent number: 7007743
    Abstract: A one-piece header tank includes side edges that are overlapped and brazed together to form a joint positioned within the interior of the tank. The tank also includes an integrally formed mounting flange that may be fabricated without jeopardizing the leak integrity of the tank.
    Type: Grant
    Filed: November 17, 2003
    Date of Patent: March 7, 2006
    Assignee: Delphi Technologies, Inc.
    Inventors: Chris A. Calhoun, Terry Joseph Hunt, David A. Southwick, Karl Paul Kroetsch, Krzysztof Wawrocki, Khalid El Moutamid, Yusuke Matsunaga, Laurent Art
  • Publication number: 20050150646
    Abstract: A heat exchanger is disclosed. A plurality of guides are integrally formed with the walls of a header tank and are used to position an oil cooler inside the tank to align a pair of fittings carried by the cooler with a pair of spaced openings in the tank.
    Type: Application
    Filed: January 8, 2004
    Publication date: July 14, 2005
    Inventors: Chris Calhoun, Terry Hunt, David Southwick, Karl Kroetsch, Krzysztof Wawrocki, Khalid Moutamid, Yusuke Matsunaga, Laurent Art
  • Publication number: 20050150641
    Abstract: A metal tank cap is integral with a reinforcing member via a narrow connection and is flared outwardly at the narrow connection portion to be over an open end of the tank simultaneously with moving the metal tubes of the core into the tank. By unbending the connection portion, the respective tank caps are deflared into the open ends of the respective tanks and the entire assembly is placed in a furnace and brazed together.
    Type: Application
    Filed: January 8, 2004
    Publication date: July 14, 2005
    Inventors: Chris Calhoun, Terry Hunt, David Southwick, Karl Kroetsch, Krzysztof Wawrocki, Khalid Moutamid, Yusuke Matsunaga, Laurent Art
  • Publication number: 20050150647
    Abstract: A secondary heat exchanger subassembly, such as a transmission oil cooler, is disposed in a metal tank of a radiator and has a pair of metal fluid fittings. Either a connector ring engages a fitting extending through the opening in the tank or a connector nut extends into the opening to threadedly engage the fitting whereby the metal fittings are held to the metal tank and inserted into a furnace for being brazed into sealed relationship with the metal tank.
    Type: Application
    Filed: January 9, 2004
    Publication date: July 14, 2005
    Inventors: Chris Calhoun, Terry Hunt, David Southwick, Karl Kroetsch, Krzysztof Wawrocki, Khalid Moutamid, Yusuke Matsunaga, Laurent Art
  • Publication number: 20050103485
    Abstract: A one-piece header tank includes side edges that are overlapped and brazed together to form a joint positioned within the interior of the tank. The tank also includes an integrally formed mounting flange that may be fabricated without jeopardizing the leak integrity of the tank.
    Type: Application
    Filed: November 17, 2003
    Publication date: May 19, 2005
    Inventors: Chris Calhoun, Terry Hunt, David Southwick, Karl Kroetsch, Krzysztof Wawrocki, Khalid Moutamid, Yusuke Matsunaga, Laurent Art
  • Publication number: 20040041275
    Abstract: A trace chip monitors a signal between a target logic chip having a data processing circuit mounted thereon and a memory chip having a memory storing data to be used by the target logic chip mounted therein, and traces an operation of the target logic chip. As the trace chip is implemented by a chip separate from the target logic chip and a memory chip, a debugging circuit need not be added to mass-produced articles when the trace chip is not mounted to the mass-produced articles. Thus, manufacturing cost of the articles can be reduced.
    Type: Application
    Filed: March 11, 2003
    Publication date: March 4, 2004
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Motoki Higashida, Yusuke Matsunaga