Abstract: A semiconductor device includes a system bus, a plurality of Central Processing Unit (CPU) cores each connected to the system bus, including a scan chain, and being assigned one or more tasks and configured to perform one of the tasks in a normal operation state, and a diagnostic test circuit connected to the system bus and capable of communicating with the plurality of the CPU cores, and configured to perform a scan test for the plurality of the CPU cores by using the scan chain. The plurality of the CPU cores outputs a test start instruction signal to the diagnostic test circuit, when the test start instruction signal is output from one of the plurality of the CPU cores, the diagnostic test circuit performs a scan test for the one of the plurality of the CPU cores in accordance with the test start instruction signal.

Abstract: A semiconductor device includes a system bus, a plurality of Central Processing Unit (CPU) cores each connected to the system bus, including a scan chain, and being assigned one or more tasks and configured to perform one of the tasks in a normal operation state, and a diagnostic test circuit connected to the system bus and capable of communicating with the plurality of the CPU cores, and configured to perform a scan test for the plurality of the CPU cores by using the scan chain. The plurality of the CPU cores outputs a test start instruction signal to the diagnostic test circuit, when the test start instruction signal is output from one of the plurality of the CPU cores, the diagnostic test circuit performs a scan test for the one of the plurality of the CPU cores in accordance with the test start instruction signal.

Abstract: Deterioration in operation performance due to a fault diagnosis is prevented. A semiconductor device 90 according to the present invention includes a plurality of CPU cores 91 to 94 each including a scan chain, and a diagnostic test circuit 95 that performs a scan test for the plurality of CPU cores 91 to 94 by using the scan chain of the CPU core. The diagnostic test circuit 95 performs a scan test for each of the plurality of CPU cores 91 to 94 in a predetermined order on a periodic basis so that execution time periods of the scan tests do not overlap each other.

Abstract: Deterioration in operation performance due to a fault diagnosis is prevented. A semiconductor device 90 according to the present invention includes a plurality of CPU cores 91 to 94 each including a scan chain, and a diagnostic test circuit 95 that performs a scan test for the plurality of CPU cores 91 to 94 by using the scan chain of the CPU core. The diagnostic test circuit 95 performs a scan test for each of the plurality of CPU cores 91 to 94 in a predetermined order on a periodic basis so that execution time periods of the scan tests do not overlap each other.

Abstract: A trace chip monitors a signal between a target logic chip having a data processing circuit mounted thereon and a memory chip having a memory storing data to be used by the target logic chip mounted therein, and traces an operation of the target logic chip. As the trace chip is implemented by a chip separate from the target logic chip and a memory chip, a debugging circuit need not be added to mass-produced articles when the trace chip is not mounted to the mass-produced articles. Thus, manufacturing cost of the articles can be reduced.

Abstract: A secondary heat exchanger subassembly, such as a transmission oil cooler, is disposed in a metal tank of a radiator and has a pair of metal fluid fittings. Either a connector ring engages a fitting extending through the opening in the tank or a connector nut extends into the opening to threadedly engage the fitting whereby the metal fittings are held to the metal tank and inserted into a furnace for being brazed into sealed relationship with the metal tank.

Abstract: A heat exchanger is disclosed. A plurality of guides are integrally formed with the walls of a header tank and are used to position an oil cooler inside the tank to align a pair of fittings carried by the cooler with a pair of spaced openings in the tank.

Abstract: A trace chip monitors a signal between a target logic chip having a data processing circuit mounted thereon and a memory chip having a memory storing data to be used by the target logic chip mounted therein, and traces an operation of the target logic chip. As the trace chip is implemented by a chip separate from the target logic chip and a memory chip, a debugging circuit need not be added to mass-produced articles when the trace chip is not mounted to the mass-produced articles. Thus, manufacturing cost of the articles can be reduced.

Abstract: A trace chip monitors a signal between a target logic chip having a data processing circuit mounted thereon and a memory chip having a memory storing data to be used by the target logic chip mounted therein, and traces an operation of the target logic chip. As the trace chip is implemented by a chip separate from the target logic chip and a memory chip, a debugging circuit need not be added to mass-produced articles when the trace chip is not mounted to the mass-produced articles. Thus, manufacturing cost of the articles can be reduced.

Abstract: A metal tank cap is integral with a reinforcing member via a narrow connection and is flared outwardly at the narrow connection portion to be over an open end of the tank simultaneously with moving the metal tubes of the core into the tank. By unbending the connection portion, the respective tank caps are deflared into the open ends of the respective tanks and the entire assembly is placed in a furnace and brazed together.

Abstract: A one-piece header tank includes side edges that are overlapped and brazed together to form a joint positioned within the interior of the tank. The tank also includes an integrally formed mounting flange that may be fabricated without jeopardizing the leak integrity of the tank.

Abstract: A heat exchanger is disclosed. A plurality of guides are integrally formed with the walls of a header tank and are used to position an oil cooler inside the tank to align a pair of fittings carried by the cooler with a pair of spaced openings in the tank.

Abstract: A metal tank cap is integral with a reinforcing member via a narrow connection and is flared outwardly at the narrow connection portion to be over an open end of the tank simultaneously with moving the metal tubes of the core into the tank. By unbending the connection portion, the respective tank caps are deflared into the open ends of the respective tanks and the entire assembly is placed in a furnace and brazed together.

Abstract: A secondary heat exchanger subassembly, such as a transmission oil cooler, is disposed in a metal tank of a radiator and has a pair of metal fluid fittings. Either a connector ring engages a fitting extending through the opening in the tank or a connector nut extends into the opening to threadedly engage the fitting whereby the metal fittings are held to the metal tank and inserted into a furnace for being brazed into sealed relationship with the metal tank.

Abstract: A one-piece header tank includes side edges that are overlapped and brazed together to form a joint positioned within the interior of the tank. The tank also includes an integrally formed mounting flange that may be fabricated without jeopardizing the leak integrity of the tank.

Abstract: A trace chip monitors a signal between a target logic chip having a data processing circuit mounted thereon and a memory chip having a memory storing data to be used by the target logic chip mounted therein, and traces an operation of the target logic chip. As the trace chip is implemented by a chip separate from the target logic chip and a memory chip, a debugging circuit need not be added to mass-produced articles when the trace chip is not mounted to the mass-produced articles. Thus, manufacturing cost of the articles can be reduced.

Abstract: A technology mapping method automatically converts a logic circuit, which does not depend on a specific circuit technology, into a circuit which uses a specific cell library by controlling a computer to optimize a pattern which is to be subjected to a matching process, based on an inclusion relationship of structures of patterns with respect to each cell.

Abstract: A technology mapping method which automatically converts a logic circuit which does not depend on a specific circuit technology into a circuit which uses a specific cell library, using a computer, is constructed to include an optimizing step of optimizing a pattern which is to be subjected to a matching process based on an inclusion relationship of structures of patterns with respect to each cell.

Abstract: A logic circuit verifying system selects independent signal lines which are positioned in an input terminal side and affects both of two internal signal lines extracted from two combinational logic circuits. The logical functions of the two internal signal lines are generated using the selected signal lines as a pseudo-input. If the logical functions match, it is determined that the two internal signal lines are equivalent to each other. According to the information about the equivalent signal lines, the equivalence of the two logic circuits can be efficiently verified.

Abstract: A method of automatically forming a combinational LSI circuit comprising two processes. A first process of computing the permissible function of each element (gate) of a given circuit. A second process of connecting a gate having a shorter signal propagation time to a gate located on a path that does not satisfy a prescribed delay time and removing the gate from the path. Thus, an arrangement of the circuit is changed and the maximum delay time of the circuit is suppressed below the prescribed delay time. This method efficiently shortens the delay time of the combinational circuit to satisfy the prescribed delay time.