Abstract: A technology mapping method automatically converts a logic circuit, which does not depend on a specific circuit technology, into a circuit which uses a specific cell library by controlling a computer to optimize a pattern which is to be subjected to a matching process, based on an inclusion relationship of structures of patterns with respect to each cell.

Abstract: A technology mapping method which automatically converts a logic circuit which does not depend on a specific circuit technology into a circuit which uses a specific cell library, using a computer, is constructed to include an optimizing step of optimizing a pattern which is to be subjected to a matching process based on an inclusion relationship of structures of patterns with respect to each cell.

Abstract: A logic circuit verifying system selects independent signal lines which are positioned in an input terminal side and affects both of two internal signal lines extracted from two combinational logic circuits. The logical functions of the two internal signal lines are generated using the selected signal lines as a pseudo-input. If the logical functions match, it is determined that the two internal signal lines are equivalent to each other. According to the information about the equivalent signal lines, the equivalence of the two logic circuits can be efficiently verified.

Abstract: A method of automatically forming a combinational LSI circuit comprising two processes. A first process of computing the permissible function of each element (gate) of a given circuit. A second process of connecting a gate having a shorter signal propagation time to a gate located on a path that does not satisfy a prescribed delay time and removing the gate from the path. Thus, an arrangement of the circuit is changed and the maximum delay time of the circuit is suppressed below the prescribed delay time. This method efficiently shortens the delay time of the combinational circuit to satisfy the prescribed delay time.

Abstract: A variable sequence determining method for determining the optimum sequence of variables in generating a dichotomy determination graph representing a logical function of a two-step logical circuit. A logical expression representing a logical function in a two-step logical circuit is converted to a sum-of-products format for simplification. Then, the number of product terms represented in the positive or negative format in each variable in the logical expression is counted, and a variable having a larger number of said product terms is assigned a higher priority in generating a dichotomy determination graph, thus determining the sequence of variables in generating a dichotomy determination graph for a two-step logical circuit.

Abstract: A method of automatically forming a combinational LSI circuit comprising two processes. A first process of computing the permissible function of each element (gate) of a given circuit. A second process of connecting a gate having a shorter signal propagation time to a gate located on a path that does not satisfy a prescribed delay time and removing the gate from the path. Thus, an arrangement of the circuit is changed and the maximum delay time of the circuit is suppressed below the prescribed delay time. This method efficiently shortens the delay time of the combinational circuit to satisfy the prescribed delay time.

Abstract: A method of expressing a logic circuit for use in a multistage logic circuit optimizing process for performing removal or scale-down modification of redundant circuit parts without changing an output logic. A tree-structure binary decision diagram representing a permissible function or a logic function is created for determining the order of input variables of a multistage logic circuit, allocating an input variable of the first order to the root, allocating the other input variables to nodes, branching the root for each logic state (1, 0) that the input variable can assume, linking branches with nodes to which an input variable of the next order is allocated and linking branches with leaves providing logic (1, 0, don't care) or logic (1, 0) of each gate and net of the circuit. Two binary decision diagrams representing permissible functions intersect to terminate branches of input variables linked with the don't-care leaf to a 0 or 1 leaf, thereby merging gates.