Patents by Inventor Yusuke Morita

Yusuke Morita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8183115
    Abstract: There is provided an SOI-MISFET including: an SOI layer; a gate electrode provided on the SOI layer interposing a gate insulator; and a first elevated layer provided higher in height from the SOI layer than the gate electrode at both sidewall sides of the gate electrode on the SOI layer so as to constitute a source and drain. Further, there is also provided a bulk-MISFET including: a gate electrode provided on a silicon substrate interposing a gate insulator thicker than the gate insulator of the SOI MISFET; and a second elevated layer configuring a source and drain provided on a semiconductor substrate at both sidewalls of the gate electrode. The first elevated layer is thicker than the second elevated layer, and the whole of the gate electrodes, part of the source and drain of the SOI-MISFET, and part of the source and drain of the bulk-MISFET are silicided.
    Type: Grant
    Filed: April 15, 2011
    Date of Patent: May 22, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Takashi Ishigaki, Ryuta Tsuchiya, Yusuke Morita, Nobuyuki Sugii, Shinichiro Kimura, Toshiaki Iwamatsu
  • Publication number: 20120099070
    Abstract: In one embodiment, a liquid crystal display device includes a first substrate and a second substrate. In the first substrate, gate lines extend in a first direction, and a first source line and a second source line extend in a second direction orthogonally crossing the first direction. A pixel electrode having a first belt-like main electrode is arranged approximately in a central portion between the first source line and the second source line and extending in the second direction. A first belt-like sub-electrode covers the gate line between the first source line and the second source line and extending in the first direction. The second substrate includes a counter electrode having a second main electrode arranged on the first and second source lines and extending in the second direction. A liquid crystal layer is held between the first substrate and the second substrate.
    Type: Application
    Filed: September 23, 2011
    Publication date: April 26, 2012
    Applicant: Toshiba Mobile Display Co., Ltd.
    Inventors: Jin HIROSAWA, Arihiro TAKEDA, Nobuko FUKUOKA, Yusuke MORITA, Kazuya DAISHI
  • Patent number: 8143668
    Abstract: Performance of a semiconductor device having a MIS transistor is improved. A semiconductor device includes: a pair of source/drain regions each formed by stacking a semiconductor layer on a main surface of a silicon substrate; a sidewall insulating film covering each sidewall of the source/drain regions; a gate electrode arranged so as to interpose a gate insulating film on the main surface of the silicon substrate at a position sandwiched by the sidewall insulating films in a plane; and extension regions formed to extend from a portion below and lateral to the gate electrode to a portion below and lateral to each of the source/drain regions, wherein a sidewall of the sidewall insulating film being adjacent to the gate insulating film and the gate electrode has an inclination of a forward tapered shape.
    Type: Grant
    Filed: June 9, 2009
    Date of Patent: March 27, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Yusuke Morita, Ryuta Tsuchiya, Takashi Ishigaki, Nobuyuki Sugii, Shinichiro Kimura
  • Publication number: 20120061774
    Abstract: Performance of a semiconductor device having a MIS transistor is improved. A semiconductor device includes: a pair of source/drain regions each formed by stacking a semiconductor layer on a main surface of a silicon substrate; a sidewall insulating film covering each sidewall of the source/drain regions; a gate electrode arranged so as to interpose a gate insulating film on the main surface of the silicon substrate at a position sandwiched by the sidewall insulating films in a plane; and extension regions formed to extend from a portion below and lateral to the gate electrode to a portion below and lateral to each of the source/drain regions, wherein a sidewall of the sidewall insulating film being adjacent to the gate insulating film and the gate electrode has an inclination of a forward tapered shape.
    Type: Application
    Filed: November 18, 2011
    Publication date: March 15, 2012
    Inventors: Yusuke Morita, Ryuta Tsuchiya, Takashi Ishigaki, Nobuyuki Sugii, Shinichiro Kimura
  • Publication number: 20120018807
    Abstract: In an SOI-MISFET that operates with low power consumption at a high speed, an element area is reduced. While a diffusion layer region of an N-conductivity type MISFET region of the SOI type MISFET and a diffusion layer region of a P-conductivity type MISFET region of the SOI type MISFET are formed as a common region, well diffusion layers that apply substrate potentials to the N-conductivity type MISFET region and the P-conductivity type MISFET region are separated from each other by an STI layer. The diffusion layer regions that are located in the N- and P-conductivity type MISFET regions) and serve as an output portion of a CMISFET are formed as a common region and directly connected by silicified metal so that the element area is reduced.
    Type: Application
    Filed: January 18, 2010
    Publication date: January 26, 2012
    Applicant: HITACHI, LTD.
    Inventors: Ryuta Tsuchiya, Nobuyuki Sugii, Yusuke Morita, Hiroyuki Yoshimoto, Takashi Ishigaki, Shinichiro Kimura
  • Patent number: 8034696
    Abstract: It is an object of the present invention to provide a method of manufacturing an SOI wafer at low cost and with high yield. It is another object of the present invention to provide a semiconductor device including also bulk type MISFETs used as high voltage regions and a method of manufacturing the same without using complicated processes and increasing the size of a semiconductor chip. The method of manufacturing a semiconductor device comprises selectively epitaxially growing a single-crystal Si layer and continuously performing the epitaxial growth without bringing a substrate temperature increased during the growth to room temperature even once. An epitaxially grown surface is then etched and planarized. The substrate temperature is then cooled down to the room temperature.
    Type: Grant
    Filed: May 18, 2007
    Date of Patent: October 11, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Ryuta Tsuchiya, Yoshinobu Kimura, Yusuke Morita
  • Publication number: 20110195566
    Abstract: There is provided an SOI-MISFET including: an SOI layer; a gate electrode provided on the SOI layer interposing a gate insulator; and a first elevated layer provided higher in height from the SOI layer than the gate electrode at both sidewall sides of the gate electrode on the SOI layer so as to constitute a source and drain. Further, there is also provided a bulk-MISFET including: a gate electrode provided on a silicon substrate interposing a gate insulator thicker than the gate insulator of the SOI MISFET; and a second elevated layer configuring a source and drain provided on a semiconductor substrate at both sidewalls of the gate electrode. A the first elevated layer is thicker than the elevated layer, and the whole of the gate electrodes, part of the source and drain of the SOI-MISFET, and part of the source and drain of the bulk-MISFET are silicided.
    Type: Application
    Filed: April 15, 2011
    Publication date: August 11, 2011
    Applicant: RENESAS ELECTRONCS CORPORATION
    Inventors: Takashi ISHIGAKI, Ryuta TSUCHIYA, Yusuke MORITA, Nobuyuki SUGII, Shinichiro KIMURA, Toshiaki IWAMATSU
  • Publication number: 20100295403
    Abstract: Provided is a permanent magnet type motor including: a rotor including a rotor core and a plurality of permanent magnets; a conducting circuit including a first electric conductor extending in an axial direction of the rotor and being disposed between permanent magnets in a circumferential direction of the rotor and a second electric conductor for connecting the first electric conductors electrically; and a stator disposed so as to be opposed to the rotor, including a stator core and an armature winding. A rotation angle is detected by measuring current flowing in the armature winding. The stator core is formed to have a shape in which, a slot pitch is defined by ?s=(2×?×Rs)/Ns, where an inner radius of the stator is represented by Rs and a number of slots is represented by Ns, a value Wsn obtained by dividing a slot opening width Ws by the slot pitch ?s satisfies “0.08?Wsn”.
    Type: Application
    Filed: May 12, 2010
    Publication date: November 25, 2010
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yusuke MORITA, Masatsugu Nakano, Sachiko Kawasaki
  • Publication number: 20100258872
    Abstract: A technique to be applied to a semiconductor device for achieving low power consumption by improving a shape at a boundary portion of a shallow trench and an SOI layer of an SOI substrate. A position (SOI edge) at which a main surface of a silicon substrate and a line extended along a side surface of an SOI layer are crossed is recessed away from a shallow-trench isolation more than a position (STI edge) at which a line extended along a sidewall of a shallow trench and a line extended along the main surface of the silicon substrate are crossed, and a corner of the silicon substrate at the STI edge has a curved surface.
    Type: Application
    Filed: April 8, 2010
    Publication date: October 14, 2010
    Inventors: Nobuyuki SUGII, Ryuta TSUCHIYA, Shinichiro KIMURA, Takashi ISHIGAKI, Yusuke MORITA, Hiroyuki YOSHIMOTO
  • Publication number: 20100258871
    Abstract: Characteristics of a semiconductor device having a FINFET are improved. The FINFET has: a channel layer arranged in an arch shape on a semiconductor substrate and formed of monocrystalline silicon; a front gate electrode formed on a part of an outside of the channel layer through a front gate insulating film; and a back gate electrode formed so as to be buried inside the channel layer through a back gate insulating film. The back gate electrode arranged inside the arch shape is arranged so as to pass through the front gate electrode.
    Type: Application
    Filed: April 13, 2010
    Publication date: October 14, 2010
    Inventors: Takashi Ishigaki, Ryuta Tsuchiya, Yusuke Morita, Nobuyuki Sugii
  • Publication number: 20100258869
    Abstract: An n well and a p well disposed at a predetermined interval on a main surface of a SOI substrate with a thin BOX layer are formed, and an nMIS formed on the p well has a pair of n-type source/drain regions formed on semiconductor layers stacked on a main surface of the SOI layer at a predetermined distance, a gate insulating film, a gate electrode and sidewalls sandwiched between the pair of n-type source/drain regions. A device isolation is formed between the n well and the p well, and a side edge portion of the device isolation extends toward a gate electrode side more than a side edge portion of the n-type source/drain region (sidewall of the BOX layer).
    Type: Application
    Filed: April 9, 2010
    Publication date: October 14, 2010
    Inventors: Yusuke MORITA, Ryuta Tsuchiya, Takashi Ishigaki, Hiroyuki Yoshimoto, Nobuyuki Sugii, Shinichiro Kimura
  • Publication number: 20100207475
    Abstract: A rotor of a rotary machine includes a rotary shaft, a rotor core fixed to a circumferential surface of the rotary shaft, a plurality of permanent magnets arranged on a circumferential surface of the rotor core at specific intervals along a circumferential direction thereof, conducting circuits arranged to surround the permanent magnets, and magnetic material pieces arranged on outer surfaces of the individual permanent magnets. Each of the conducting circuits includes a pair of first conductor sections arranged between magnetic poles formed by the adjacent permanent magnets and a pair of second conductor sections electrically connecting the first conductor sections.
    Type: Application
    Filed: September 15, 2009
    Publication date: August 19, 2010
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Sachiko Kawasaki, Hiroyuki Akita, Masatsugu Nakano, Yusuke Morita
  • Publication number: 20100123979
    Abstract: By using switching power supplies a, b, and n, which have detection function of over-current, over-voltage and low voltage, in the case where a short-circuit occurred in a load which is connected to output of a switching power supply, and in the case where a MOSFET of the switching power supply is in a short-circuit state and broken, a main power is forced to be off, and a failure log of the switching power supply is stored in a non-volatile memory unit EEPROM; and also in the case where the main power was turned off and on, even if an abnormal log of the switching power supply logged in the non-volatile memory unit, reclosing of the main power is suppressed and which of the switching power supply occurred failure is notified to the outside.
    Type: Application
    Filed: November 10, 2009
    Publication date: May 20, 2010
    Inventors: Michinori Naito, Naoyuki Todoroki, Kenta Ota, Junya Ide, Yusuke Morita
  • Publication number: 20090309159
    Abstract: Performance of a semiconductor device having a MIS transistor is improved. A semiconductor device includes: a pair of source/drain regions each formed by stacking a semiconductor layer on a main surface of a silicon substrate; a sidewall insulating film covering each sidewall of the source/drain regions; a gate electrode arranged so as to interpose a gate insulating film on the main surface of the silicon substrate at a position sandwiched by the sidewall insulating films in a plane; and extension regions formed to extend from a portion below and lateral to the gate electrode to a portion below and lateral to each of the source/drain regions, wherein a sidewall of the sidewall insulating film being adjacent to the gate insulating film and the gate electrode has an inclination of a forward tapered shape.
    Type: Application
    Filed: June 9, 2009
    Publication date: December 17, 2009
    Inventors: Yusuke MORITA, Ryuta TSUCHIYA, Takashi ISHIGAKI, Nobuyuki SUGII, Shinichiro KIMURA
  • Publication number: 20090096036
    Abstract: There is provided an SOI-MISFET including: an SOI layer; a gate electrode provided on the SOI layer interposing a gate insulator; and a first elevated layer provided higher in height from the SOI layer than the gate electrode at both sidewall sides of the gate electrode on the SOI layer so as to constitute a source and drain. Further, there is also provided a bulk-MISFET including: a gate electrode provided on a silicon substrate interposing a gate insulator thicker than the gate insulator of the SOI MISFET; and a second elevated layer configuring a source and drain provided on a semiconductor substrate at both sidewalls of the gate electrode. A the first elevated layer is thicker than the elevated layer, and the whole of the gate electrodes, part of the source and drain of the SOI-MISFET, and part of the source and drain of the bulk-MISFET are silicided.
    Type: Application
    Filed: October 9, 2008
    Publication date: April 16, 2009
    Inventors: Takashi ISHIGAKI, Ryuta Tsuchiya, Yusuke Morita, Nobuyuki Sugii, Shinichiro Kimura, Toshiaki Iwamatsu
  • Publication number: 20080258218
    Abstract: A MIS transistor having an inclined stacked source/drain structure increased in speed is provided. The MIS transistor comprises: a gate electrode formed on a substrate; a first sidewall insulating film formed on the substrate and along a sidewall of the gate electrode; source/drain semiconductor regions formed on a main surface of the substrate and respectively having one edge positioned under the sidewall of the gate electrode; a first stacked layer formed on the source/drain semiconductor regions and in contact with the first sidewall insulating film; a second sidewall insulating film formed on the stacked layer and in contact with the first sidewall insulating film; and a second stacked layer formed on the first stacked layer and in contact with the second sidewall insulating layer.
    Type: Application
    Filed: April 17, 2008
    Publication date: October 23, 2008
    Inventors: Yusuke Morita, Yoshinobu Kimura, Ryuta Tsuchiya, Nobuyuki Sugii, Shinichiro Kimura
  • Publication number: 20070290264
    Abstract: The invention aims at increasing an effect of a strain applying technique for enhancing transistor performance in a fully depleted silicon-on-insulator (FDSOI) type transistor having a thin buried oxide (BOX) film. In an FDSOI type transistor having a very thin SOI structure (6), a stress generating region is formed on a back face side (5) of a very thin BOX layer (4) in order to apply strains to portions in which channels are intended to be formed. Desired portions on a back face side of the BOX layer (4) are amorphized by performing ion implantation, and are then recrystallized by performing a heat treatment in a state where a stress applying film (3) is formed, thereby transferring stresses from the stress applying film (3) to the portions in which the channels are intended to be formed. Thus, the stress generating region is formed.
    Type: Application
    Filed: February 13, 2007
    Publication date: December 20, 2007
    Inventors: Nobuyuki Sugii, Ryuta Tsuchiya, Yusuke Morita
  • Publication number: 20070266933
    Abstract: It is an object of the present invention to provide a method of manufacturing an SOI wafer at low cost and with high yield. It is another object of the present invention to provide a semiconductor device including also bulk type MISFETs used as high voltage regions and a method of manufacturing the same without using complicated processes and increasing the size of a semiconductor chip. The method of manufacturing a semiconductor device comprises selectively epitaxially growing a single-crystal Si layer and continuously performing the epitaxial growth without bringing a substrate temperature increased during the growth to room temperature even once. An epitaxially grown surface is then etched and planarized. The substrate temperature is then cooled down to the room temperature.
    Type: Application
    Filed: May 18, 2007
    Publication date: November 22, 2007
    Inventors: Ryuta Tsuchiya, Yoshinobu Kimura, Yusuke Morita
  • Patent number: 5513688
    Abstract: Dispersion strengthened metal matrix composites are produced by stirring a mixed solid-liquid phase slurry as a dispersing medium under a reduced pressure, adding a dispersion strengthening material to the dispersing medium, and continuing the stirring under the reduced pressure till the dispersion strengthening material is uniformly dispersed in the dispersing medium.
    Type: Grant
    Filed: September 21, 1993
    Date of Patent: May 7, 1996
    Assignee: Rheo-Technology, Ltd.
    Inventors: Yusuke Morita, Kazuhiro Ozawa, Akihiko Nanba
  • Patent number: 5498656
    Abstract: Proposed is a polyvinyl alcohol molding resin composition exhibiting excellent workability in the molding procedure by extrusion and injection and capable of giving molded articles, e.g., films and sheets, having excellent properties in respect of good appearance and excellent resistance against coloration by heating. The molding resin composition comprises a polyvinyl alcohol and a limited amount of an additive ingredient which is an alkali or alkaline earth metal salt of organic sulfonic acid, e.g., sodium and calcium dodecylbenzene sulfonates, a polyoxyethylene ester of phosphoric acid or a combination thereof.
    Type: Grant
    Filed: March 31, 1995
    Date of Patent: March 12, 1996
    Assignees: Shin-Etsu Polymer Co., Ltd., Akishima Chemical Industries Co., Ltd.
    Inventors: Yusuke Morita, Masami Fukushima, Fumio Gotou, Shigeo Aoki