Patents by Inventor Yusuke Oshiki
Yusuke Oshiki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230354610Abstract: According to one embodiment, a method for manufacturing a semiconductor memory device includes simultaneously forming a plurality of first holes and a plurality of second holes in a stacked body. The stacked body includes a plurality of first layers and a plurality of second layers. The method includes etching a portion between the second holes next to each other in the stacked body, and connecting at least two or more second holes to form a groove. The method includes forming a film including a charge storage film on a sidewall of the first holes. The method includes forming a channel film on a sidewall of the film including the charge storage film.Type: ApplicationFiled: July 3, 2023Publication date: November 2, 2023Applicant: Kioxia CorporationInventors: Hirotaka TSUDA, Yusuke OSHIKI
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Patent number: 11744074Abstract: According to one embodiment, a method for manufacturing a semiconductor memory device includes simultaneously forming a plurality of first holes and a plurality of second holes in a stacked body. The stacked body includes a plurality of first layers and a plurality of second layers. The method includes etching a portion between the second holes next to each other in the stacked body, and connecting at least two or more second holes to form a groove. The method includes forming a film including a charge storage film on a sidewall of the first holes. The method includes forming a channel film on a sidewall of the film including the charge storage film.Type: GrantFiled: April 7, 2022Date of Patent: August 29, 2023Assignee: Kioxia CorporationInventors: Hirotaka Tsuda, Yusuke Oshiki
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Publication number: 20220231045Abstract: According to one embodiment, a method for manufacturing a semiconductor memory device includes simultaneously forming a plurality of first holes and a plurality of second holes in a stacked body. The stacked body includes a plurality of first layers and a plurality of second layers. The method includes etching a portion between the second holes next to each other in the stacked body, and connecting at least two or more second holes to form a groove. The method includes forming a film including a charge storage film on a sidewall of the first holes. The method includes forming a channel film on a sidewall of the film including the charge storage film.Type: ApplicationFiled: April 7, 2022Publication date: July 21, 2022Applicant: Kioxia CorporationInventors: Hirotaka TSUDA, Yusuke OSHIKI
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Publication number: 20220199533Abstract: A semiconductor storage device according to an embodiment includes: a first stacked body including a plurality of first electrode layers and a plurality of first insulating layers that are alternately stacked on a substrate in a first direction perpendicular to the substrate; a plurality of semiconductor films penetrating the first stacked body in the first direction; a second stacked body including a plurality of second electrode layers and a plurality of second insulating layers that are alternately stacked on the first stacked body in the first direction; and a plurality of contact plugs penetrating the second stacked body in the first direction and separately connected to the respective plurality of semiconductor films and the respective plurality of second electrode layers.Type: ApplicationFiled: March 10, 2022Publication date: June 23, 2022Applicant: Kioxia CorporationInventor: Yusuke OSHIKI
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Patent number: 11322513Abstract: According to one embodiment, a method for manufacturing a semiconductor memory device includes simultaneously forming a plurality of first holes and a plurality of second holes in a stacked body. The stacked body includes a plurality of first layers and a plurality of second layers. The method includes etching a portion between the second holes next to each other in the stacked body, and connecting at least two or more second holes to form a groove. The method includes forming a film including a charge storage film on a sidewall of the first holes. The method includes forming a channel film on a sidewall of the film including the charge storage film.Type: GrantFiled: February 4, 2020Date of Patent: May 3, 2022Assignee: Kioxia CorporationInventors: Hirotaka Tsuda, Yusuke Oshiki
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Publication number: 20200176469Abstract: According to one embodiment, a method for manufacturing a semiconductor memory device includes simultaneously forming a plurality of first holes and a plurality of second holes in a stacked body. The stacked body includes a plurality of first layers and a plurality of second layers. The method includes etching a portion between the second holes next to each other in the stacked body, and connecting at least two or more second holes to form a groove. The method includes forming a film including a charge storage film on a sidewall of the first holes. The method includes forming a channel film on a sidewall of the film including the charge storage film.Type: ApplicationFiled: February 4, 2020Publication date: June 4, 2020Applicant: TOSHIBA MEMORY CORPORATIONInventors: Hirotaka TSUDA, Yusuke Oshiki
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Patent number: 10593694Abstract: According to one embodiment, a method for manufacturing a semiconductor memory device includes simultaneously forming a plurality of first holes and a plurality of second holes in a stacked body. The stacked body includes a plurality of first layers and a plurality of second layers. The method includes etching a portion between the second holes next to each other in the stacked body, and connecting at least two or more second holes to form a groove. The method includes forming a film including a charge storage film on a sidewall of the first holes. The method includes forming a channel film on a sidewall of the film including the charge storage film.Type: GrantFiled: October 17, 2018Date of Patent: March 17, 2020Assignee: Toshiba Memory CorporationInventors: Hirotaka Tsuda, Yusuke Oshiki
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Patent number: 10535677Abstract: A semiconductor memory device according to an embodiment includes: a semiconductor substrate; an insulating film provided on the semiconductor substrate; a conductive layer group including at least two conductive layers; a stacked body provided on the conductive layer group and including a plurality of films stacked; a memory film provided in a hole, the hole penetrating the stacked body and a part of the conductive layer group; and a slit splitting the stacked body and terminating at a position deeper than a contact portion between the conductive layer group and the memory film. The conductive layer group has a band-shaped part projecting to the stacked body side at a portion of the hole, and a groove part recessed to the semiconductor substrate side at a portion under the slit.Type: GrantFiled: August 17, 2018Date of Patent: January 14, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventor: Yusuke Oshiki
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Publication number: 20190287987Abstract: A semiconductor memory device according to an embodiment includes: a semiconductor substrate; an insulating film provided on the semiconductor substrate; a conductive layer group including at least two conductive layers; a stacked body provided on the conductive layer group and including a plurality of films stacked; a memory film provided in a hole, the hole penetrating the stacked body and a part of the conductive layer group; and a slit splitting the stacked body and terminating at a position deeper than a contact portion between the conductive layer group and the memory film. The conductive layer group has a band-shaped part projecting to the stacked body side at a portion of the hole, and a groove part recessed to the semiconductor substrate side at a portion under the slit.Type: ApplicationFiled: August 17, 2018Publication date: September 19, 2019Applicant: TOSHIBA MEMORY CORPORATIONInventor: Yusuke OSHIKI
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Patent number: 10290595Abstract: According to an embodiment, a semiconductor memory device includes a substrate, an insulating film, a plurality of conductive films, an insulating member, a plurality of stacked bodies, and a first member. The insulating member is provided on the insulating film, is positioned between the conductive films in a first direction along the substrate, and extends in a second direction along the substrate, the second direction crossing the first direction. The first member is provided on the insulating member, is positioned between the stacked bodies in the first direction, and extends in a stacking direction of the plurality of electrode films of the stacked bodies. A width in the first direction of the insulating member is larger than a width in the first direction of the first member.Type: GrantFiled: September 6, 2017Date of Patent: May 14, 2019Assignee: Toshiba Memory CorporationInventor: Yusuke Oshiki
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Publication number: 20190051663Abstract: According to one embodiment, a method for manufacturing a semiconductor memory device includes simultaneously forming a plurality of first holes and a plurality of second holes in a stacked body. The stacked body includes a plurality of first layers and a plurality of second layers. The method includes etching a portion between the second holes next to each other in the stacked body, and connecting at least two or more second holes to form a groove. The method includes forming a film including a charge storage film on a sidewall of the first holes. The method includes forming a channel film on a sidewall of the film including the charge storage film.Type: ApplicationFiled: October 17, 2018Publication date: February 14, 2019Applicant: Toshiba Memory CorporationInventors: Hirotaka TSUDA, Yusuke Oshiki
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Patent number: 10153164Abstract: A method for manufacturing a semiconductor device includes forming a mask layer including a) one metal from tungsten, tantalum, zirconium, hafnium, molybdenum, niobium, ruthenium, osmium, rhenium, and iridium, b) boron, and c) carbon on a layer to be etched. The mask layer is patterned. A hole or a groove is formed in the layer to be etched by performing dry etching on the layer to be etched using the patterned mask layer. The mask layer includes a first region and a second region. The first region includes boron and the second region includes boron such that a density of boron in the second region is different from a density of boron in the first region, or the first region includes carbon and the second region includes carbon such that a density of carbon in the second region is different from a density of carbon in the first region.Type: GrantFiled: July 27, 2017Date of Patent: December 11, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Shinichi Nakao, Shunsuke Ochiai, Yusuke Oshiki, Kei Watanabe, Mitsuhiro Omura
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Patent number: 10141329Abstract: According to one embodiment, a method for manufacturing a semiconductor memory device includes simultaneously forming a plurality of first holes and a plurality of second holes in a stacked body. The stacked body includes a plurality of first layers and a plurality of second layers. The method includes etching a portion between the second holes next to each other in the stacked body, and connecting at least two or more second holes to form a groove. The method includes forming a film including a charge storage film on a sidewall of the first holes. The method includes forming a channel film on a sidewall of the film including the charge storage film.Type: GrantFiled: February 23, 2017Date of Patent: November 27, 2018Assignee: Toshiba Memory CorporationInventors: Hirotaka Tsuda, Yusuke Oshiki
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Publication number: 20180277499Abstract: According to an embodiment, a semiconductor memory device includes a substrate, an insulating film, a plurality of conductive films, an insulating member, a plurality of stacked bodies, and a first member. The insulating member is provided on the insulating film, is positioned between the conductive films in a first direction along the substrate, and extends in a second direction along the substrate, the second direction crossing the first direction. The first member is provided on the insulating member, is positioned between the stacked bodies in the first direction, and extends in a stacking direction of the plurality of electrode films of the stacked bodies. A width in the first direction of the insulating member is larger than a width in the first direction of the first member.Type: ApplicationFiled: September 6, 2017Publication date: September 27, 2018Applicant: Toshiba Memory CorporationInventor: Yusuke OSHIKI
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Publication number: 20180197874Abstract: The semiconductor device includes a base material, a plurality of electrode layers, and a first contact portion. The plurality of electrode layers are provided above the base material and arranged along a first direction. The first contact portion extends through the plurality of electrode layers in the first direction. The plurality of electrode layers include a first electrode layer and a second electrode layer. The second electrode layer is positioned between the base material and the first electrode layer. The first contact portion includes a first conductive portion and a first insulating portion. The first conductive portion extends in the first direction, is electrically connected to the first electrode layer, and is insulated from the second electrode layer. The first insulating portion is provided between the base material and the first conductive portion and extends through the second electrode layer in the first direction.Type: ApplicationFiled: March 9, 2017Publication date: July 12, 2018Applicant: Toshiba Memory CorporationInventors: Yusuke OSHIKI, Masanobu Baba
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Publication number: 20180166276Abstract: A method for manufacturing a semiconductor device includes forming a mask layer including a) one metal from tungsten, tantalum, zirconium, hafnium, molybdenum, niobium, ruthenium, osmium, rhenium, and iridium, b) boron, and c) carbon on a layer to be etched. The mask layer is patterned. A hole or a groove is formed in the layer to be etched by performing dry etching on the layer to be etched using the patterned mask layer. The mask layer includes a first region and a second region. The first region includes boron and the second region includes boron such that a density of boron in the second region is different from a density of boron in the first region, or the first region includes carbon and the second region includes carbon such that a density of carbon in the second region is different from a density of carbon in the first region.Type: ApplicationFiled: July 27, 2017Publication date: June 14, 2018Applicant: TOSHIBA MEMORY CORPORATONInventors: Shinichi NAKAO, Shunsuke OCHIAI, Yusuke OSHIKI, Kei WATANABE, Mitsuhiro OMURA
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Patent number: 9754793Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes forming a mask layer on a layer to be etched, the mask layer containing tungsten and boron, a composition ratio of the tungsten being not less than 30%, patterning the mask layer, and performing a dry etching to the layer to be etched using the mask layer being patterned, and forming a hole or a slit in the layer to be etched.Type: GrantFiled: December 12, 2016Date of Patent: September 5, 2017Assignee: TOSHIBA MEMORY CORPORATIONInventors: Shinichi Nakao, Shunsuke Ochiai, Yusuke Oshiki, Kei Watanabe, Mitsuhiro Omura, Kosuke Horibe, Atsuko Sakata, Junichi Wada, Soichi Yamazaki, Masayuki Kitamura, Yuya Matsubara
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Publication number: 20170162596Abstract: According to one embodiment, a method for manufacturing a semiconductor memory device includes simultaneously forming a plurality of first holes and a plurality of second holes in a stacked body. The stacked body includes a plurality of first layers and a plurality of second layers. The method includes etching a portion between the second holes next to each other in the stacked body, and connecting at least two or more second holes to form a groove. The method includes forming a film including a charge storage film on a sidewall of the first holes. The method includes forming a channel film on a sidewall of the film including the charge storage film.Type: ApplicationFiled: February 23, 2017Publication date: June 8, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Hirotaka TSUDA, Yusuke OSHIKI
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Patent number: 9627401Abstract: According to one embodiment, a method for manufacturing a semiconductor memory device includes simultaneously forming a plurality of first holes and a plurality of second holes in a stacked body. The stacked body includes a plurality of first layers and a plurality of second layers. The method includes etching a portion between the second holes next to each other in the stacked body, and connecting at least two or more second holes to form a groove. The method includes forming a film including a charge storage film on a sidewall of the first holes. The method includes forming a channel film on a sidewall of the film including the charge storage film.Type: GrantFiled: March 4, 2015Date of Patent: April 18, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Hirotaka Tsuda, Yusuke Oshiki
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Patent number: 9620366Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes forming a mask layer on a layer to be etched. The mask layer contains at least one type of a metal, boron, and carbon. The metal is selected from a group including tungsten, tantalum, zirconium, hafnium, molybdenum, niobium, ruthenium, osmium, rhenium and iridium. A composition ratio of the metal is higher than a composition ratio of the boron and a composition ratio of the carbon. The method includes making a hole or a slit in the layer to be etched by performing a dry etching to the layer to be etched using the mask layer being patterned.Type: GrantFiled: June 10, 2016Date of Patent: April 11, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Shinichi Nakao, Shunsuke Ochiai, Yusuke Oshiki, Kei Watanabe, Mitsuhiro Omura