Patents by Inventor Yusuke Oshiki
Yusuke Oshiki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9627401Abstract: According to one embodiment, a method for manufacturing a semiconductor memory device includes simultaneously forming a plurality of first holes and a plurality of second holes in a stacked body. The stacked body includes a plurality of first layers and a plurality of second layers. The method includes etching a portion between the second holes next to each other in the stacked body, and connecting at least two or more second holes to form a groove. The method includes forming a film including a charge storage film on a sidewall of the first holes. The method includes forming a channel film on a sidewall of the film including the charge storage film.Type: GrantFiled: March 4, 2015Date of Patent: April 18, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Hirotaka Tsuda, Yusuke Oshiki
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Patent number: 9620366Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes forming a mask layer on a layer to be etched. The mask layer contains at least one type of a metal, boron, and carbon. The metal is selected from a group including tungsten, tantalum, zirconium, hafnium, molybdenum, niobium, ruthenium, osmium, rhenium and iridium. A composition ratio of the metal is higher than a composition ratio of the boron and a composition ratio of the carbon. The method includes making a hole or a slit in the layer to be etched by performing a dry etching to the layer to be etched using the mask layer being patterned.Type: GrantFiled: June 10, 2016Date of Patent: April 11, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Shinichi Nakao, Shunsuke Ochiai, Yusuke Oshiki, Kei Watanabe, Mitsuhiro Omura
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Publication number: 20170092505Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes forming a mask layer on a layer to be etched, the mask layer containing tungsten and boron, a composition ratio of the tungsten being not less than 30%, patterning the mask layer, and performing a dry etching to the layer to be etched using the mask layer being patterned, and forming a hole or a slit in the layer to be etched.Type: ApplicationFiled: December 12, 2016Publication date: March 30, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Shinichi NAKAO, Shunsuke OCHIAI, Yusuke OSHIKI, Kei WATANABE, Mitsuhiro OMURA, Kosuke HORIBE, Atsuko SAKATA, Junichi WADA, Soichi YAMAZAKI, Masayuki KITAMURA, Yuya MATSUBARA
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Publication number: 20160365249Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes forming a mask layer on a layer to be etched. The mask layer contains at least one type of a metal, boron, and carbon. The metal is selected from a group including tungsten, tantalum, zirconium, hafnium, molybdenum, niobium, ruthenium, osmium, rhenium and iridium. A composition ratio of the metal is higher than a composition ratio of the boron and a composition ratio of the carbon. The method includes making a hole or a slit in the layer to be etched by performing a dry etching to the layer to be etched using the mask layer being patterned.Type: ApplicationFiled: June 10, 2016Publication date: December 15, 2016Applicant: Kabushiki Kaisha ToshibaInventors: Shinichi Nakao, Shunsuke Ochiai, Yusuke Oshiki, Kei Watanabe, Mitsuhiro Omura
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Publication number: 20160126252Abstract: According to one embodiment, a method for manufacturing a semiconductor memory device includes simultaneously forming a plurality of first holes and a plurality of second holes in a stacked body. The stacked body includes a plurality of first layers and a plurality of second layers. The method includes etching a portion between the second holes next to each other in the stacked body, and connecting at least two or more second holes to form a groove. The method includes forming a film including a charge storage film on a sidewall of the first holes. The method includes forming a channel film on a sidewall of the film including the charge storage film.Type: ApplicationFiled: March 4, 2015Publication date: May 5, 2016Inventors: Hirotaka TSUDA, Yusuke OSHIKI
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Publication number: 20160071957Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes forming a mask layer above an etching object layer, the mask layer having a plurality of first layers, a plurality of spaces each provided between the first layers, and an opening part penetrating the first layers and communicating with the spaces; and dry etching the etching object layer of a different kind of material from a kind of material of the first layers using the mask layer.Type: ApplicationFiled: March 10, 2015Publication date: March 10, 2016Inventors: Yusuke OSHIKI, Mitsuhiro OMURA
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Patent number: 8759205Abstract: According to one embodiment, a method for manufacturing a semiconductor device, wherein an amorphous semiconductor film comprising a microcrystal is annealed using a microwave, to crystallize the amorphous semiconductor film comprising the microcrystal using the microcrystal as a nucleus.Type: GrantFiled: September 16, 2010Date of Patent: June 24, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Tomonori Aoyama, Yusuke Oshiki, Kiyotaka Miyano
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Patent number: 8383452Abstract: In one embodiment, a method for manufacturing a semiconductor device is disclosed. The method can include depositing a first amorphous film having a first impurity, depositing a third amorphous lower-layer film on the first amorphous film, forming microcrystals on the third amorphous lower-layer film, depositing a third amorphous upper-layer film on the third amorphous lower-layer film to cover the microcrystals, depositing a second amorphous film having a second impurity on the third amorphous upper-layer film, and radiating microwaves to crystallize the third amorphous lower-layer film and the third amorphous upper-layer film to form a third crystal layer, and crystallize the first amorphous film and the second amorphous film to form a first crystal layer and a second crystal layer.Type: GrantFiled: January 31, 2011Date of Patent: February 26, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Tomonori Aoyama, Kiyotaka Miyano, Yusuke Oshiki
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Patent number: 8377732Abstract: In one embodiment, a method of manufacturing a back side illuminated imaging device includes forming a semiconductor detection device and a peripheral circuit device on a semiconductor substrate, and bonding the semiconductor substrate onto a holding substrate via the semiconductor detection device and the peripheral circuit device. The method further includes removing the semiconductor substrate from the holding substrate to transfer the semiconductor detection device and the peripheral circuit device onto the holding substrate. The method further includes forming an amorphous semiconductor layer in which impurities are introduced, on the semiconductor detection device transferred onto the holding substrate, and annealing the amorphous semiconductor layer by using a microwave.Type: GrantFiled: September 21, 2010Date of Patent: February 19, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Yusuke Oshiki, Kiyotaka Miyano
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Patent number: 8148717Abstract: A manufacturing method for semiconductor device includes: forming an opening, in a surface of a semiconductor substrate being composed of first atom, the opening having an opening ratio y to an area of the surface of the semiconductor substrate ranging from 5 to 30%; forming an epitaxial layer in the opening, the epitaxial layer being made of a mixed crystal containing a second atom in a concentration ranging from 15 to 25%, and the second atom having a lattice constant different from a lattice constant of the first atom; implanting impurity ion into the epitaxial layer; and performing activation annealing at a predetermined temperature T, the predetermined temperature T being equal to or higher than 1150° C. and satisfies a relationship of y?1E-5exp (21541/T).Type: GrantFiled: January 28, 2011Date of Patent: April 3, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Takayuki Ito, Yusuke Oshiki, Kouji Matsuo, Kenichi Yoshino, Takaharu Itani, Takuo Ohashi, Toshihiko Iinuma, Kiyotaka Miyano, Kunihiro Miyazaki
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Publication number: 20120025200Abstract: In one embodiment, a method for manufacturing a semiconductor device is disclosed. The method can include depositing a first amorphous film having a first impurity, depositing a third amorphous lower-layer film on the first amorphous film, forming microcrystals on the third amorphous lower-layer film, depositing a third amorphous upper-layer film on the third amorphous lower-layer film to cover the microcrystals, depositing a second amorphous film having a second impurity on the third amorphous upper-layer film, and radiating microwaves to crystallize the third amorphous lower-layer film and the third amorphous upper-layer film to form a third crystal layer, and crystallize the first amorphous film and the second amorphous film to form a first crystal layer and a second crystal layer.Type: ApplicationFiled: January 31, 2011Publication date: February 2, 2012Inventors: Tomonori Aoyama, Kiyotaka Miyano, Yusuke Oshiki
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Publication number: 20110215333Abstract: According to one embodiment, a method for manufacturing a semiconductor device, wherein an amorphous semiconductor film comprising a microcrystal is annealed using a microwave, to crystallize the amorphous semiconductor film comprising the microcrystal using the microcrystal as a nucleus.Type: ApplicationFiled: September 16, 2010Publication date: September 8, 2011Inventors: Tomonori AOYAMA, Yusuke Oshiki, Kiyotaka Miyano
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Publication number: 20110159634Abstract: In one embodiment, a method of manufacturing a back side illuminated imaging device includes forming a semiconductor detection device and a peripheral circuit device on a semiconductor substrate, and bonding the semiconductor substrate onto a holding substrate via the semiconductor detection device and the peripheral circuit device. The method further includes removing the semiconductor substrate from the holding substrate to transfer the semiconductor detection device and the peripheral circuit device onto the holding substrate. The method further includes forming an amorphous semiconductor layer in which impurities are introduced, on the semiconductor detection device transferred onto the holding substrate, and annealing the amorphous semiconductor layer by using a microwave.Type: ApplicationFiled: September 21, 2010Publication date: June 30, 2011Inventors: Yusuke Oshiki, Kiyotaka Miyano
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Publication number: 20110127578Abstract: A manufacturing method for semiconductor device includes: forming an opening, in a surface of a semiconductor substrate being composed of first atom, the opening having an opening ratio y to an area of the surface of the semiconductor substrate ranging from 5 to 30%; forming an epitaxial layer in the opening, the epitaxial layer being made of a mixed crystal containing a second atom in a concentration ranging from 15 to 25%, and the second atom having a lattice constant different from a lattice constant of the first atom; implanting impurity ion into the epitaxial layer; and performing activation annealing at a predetermined temperature T, the predetermined temperature T being equal to or higher than 1150° C. and satisfies a relationship of y?1E-5exp (21541/T).Type: ApplicationFiled: January 28, 2011Publication date: June 2, 2011Applicant: Kabushiki Kaisha ToshibaInventors: Takayuki Ito, Yusuke Oshiki, Kouji Matsuo, Kenichi Yoshino, Takaharu Itani, Takuo Ohashi, Toshihiko Iinuma, Kiyotaka Miyano, Kunihiro Miyazaki
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Patent number: 7902030Abstract: A manufacturing method for semiconductor device includes: forming an opening, in a surface of a semiconductor substrate being composed of first atom, the opening having an opening ratio y to an area of the surface of the semiconductor substrate ranging from 5 to 30%; forming an epitaxial layer in the opening, the epitaxial layer being made of a mixed crystal containing a second atom in a concentration ranging from 15 to 25%, and the second atom having a lattice constant different from a lattice constant of the first atom; implanting impurity ion into the epitaxial layer; and performing activation annealing at a predetermined temperature T, the predetermined temperature T being equal to or higher than 1150° C. and satisfies a relationship of y?1E-5exp(21541/T).Type: GrantFiled: June 12, 2009Date of Patent: March 8, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Takayuki Ito, Yusuke Oshiki, Kouji Matsuo, Kenichi Yoshino, Takaharu Itani, Takuo Ohashi, Toshihiko Iinuma, Kiyotaka Miyano, Kunihiro Miyazaki
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Publication number: 20090309133Abstract: A manufacturing method for semiconductor device includes: forming an opening, in a surface of a semiconductor substrate being composed of first atom, the opening having an opening ratio y to an area of the surface of the semiconductor substrate ranging from 5 to 30%; forming an epitaxial layer in the opening, the epitaxial layer being made of a mixed crystal containing a second atom in a concentration ranging from 15 to 25%, and the second atom having a lattice constant different from a lattice constant of the first atom; implanting impurity ion into the epitaxial layer; and performing activation annealing at a predetermined temperature T, the predetermined temperature T being equal to or higher than 1150° C. and satisfies a relationship of y?1E-5exp(21541/T).Type: ApplicationFiled: June 12, 2009Publication date: December 17, 2009Inventors: Takayuki Ito, Yusuke Oshiki, Kouji Matsuo, Kenichi Yoshino, Takaharu Itani, Takuo Ohashi, Toshihiko Iinuma, Kiyotaka Miyano, Kunihiro Miyazaki