Abstract: A display driver includes holding circuits outputting data of n bits (n?2), a multiplexer receiving data output from the holding circuits and time sharingly outputting the data in normal operation, and a D/A converter, having converting input terminals, converting based on data of n bits input via the converting input terminals and outputting gray scale voltage, wherein each holding circuit includes latch circuits latching each bit data, the multiplexer includes multiplexer output terminals, and, during testing, each holding circuit serially outputs the holding circuit data as serial output from the output from the n-th latch circuit, the multiplexer time sharingly outputs the serial output from the n-th multiplexer output terminal, the serial output is input into each converting input terminal via the n-th multiplexer output terminal, and the D/A converter converts every time each bit data of the serial output is input into the converting input terminals.

Abstract: A display driver including: a hold circuit; a D/A converter converting display data from the hold circuit; and an output selector receiving a gray scale voltage based on output of the converter into a first input terminal and outputting a drive voltage to a drive voltage output terminal, the hold circuit including first to n-th latch circuits. In normal operations, the hold circuit outputs data latched in the latch circuits to the converter. In test operations, the hold circuit serially outputs data latched in the latch circuits as serial output data from the n-th latch circuit. The output selector has a second input terminal receiving the serial output data, outputs to the drive voltage output terminal the gray scale voltage inputted into the first input terminal in normal operations, and a voltage based on the serial output data from the hold circuit into the second input terminal in test operations.

Abstract: An optical network unit is associated with a multi-wavelength optical fiber communications system carrying low-power digital signals bidirectionally transmitted at a first and a second wavelength and a high-power analog video signal transmitted at a third wavelength. The unit comprises a housing having a connection for the optical fiber; and an optical filter, first and second optical units, and a beam splitter mounted in the housing. The optical filter is interposed between the fiber termination and the second optical unit, and is adapted to block light of the third wavelength but bidirectionally transmit light of the first and second wavelengths. The system is readily implemented, and any combination of the data and video services may be selected. A high level of skill is not required for changing the combination of services procured.

Abstract: In a display data RAM, a group of memory cells for storing grayscale data for two lines are disposed within an output pad pitch L of a display driver circuit, and at least two groups of the memory cells are arranged in a direction perpendicular to the direction in which the output pads are arranged. The grayscale data for two lines is read at a time from the display data RAM. Latch circuits latch the grayscale data for four lines based on first and second clock signals. A selector circuit selectively outputs the grayscale data for consecutive three lines from among the grayscale data latched in the latch circuit. An MLS signal conversion circuit performs MLS operation in which three lines are simultaneously selected, based on the selectively output grayscale data for three lines. A signal electrode driver circuit outputs a drive voltage to the output pads based on the MLS operation results.

Abstract: The present invention provides a display driver circuit having a simple configuration due to a decrease in the number of voltage levels and capable of preventing deterioration of contrast ratio in display drive by using MLS, an electro-optical device, and a display drive method. First to fourth bits of grayscale data corresponding to a display pattern for three lines are supplied to each ROM. The ROMs decode and output 4MLS operation results for a display pattern defined by the first to fourth bits of the grayscale data and a dummy display-pattern corresponding to the display pattern based on orthogonal functions defined by combinations of a scan pattern and a dummy scan pattern of a virtual electrode based on a field signal.

Abstract: In the case the die cut label sheet is mounted, by detection of threshold voltage of output signal of the photo sensor, each label provisionally adhered to a front surface of the die cut label sheet is fed to a print start position. In the case the unfixed-length roll sheet is mounted, if the feeding speed is less than 40 mm/sec, by detection of threshold voltage of output signal of the photo sensor, the feeding state of unfixed-length roll sheet is judged, or if the feeding speed is not less than 40 mm/sec, on the basis of voltage change for the predetermined potential difference portion of output signal of the photo sensor, the feeding state of unfixed-length roll sheet is judged.

Abstract: A driver IC including: a plurality of output pads; and a plurality of signal switch circuits, each of the signal circuits being provided on one of signal paths respectively connected to the output pads, wherein each of the signal switch circuits switches between a first state (or a use state) in which a signal from an upstream side of the signal path is allowed to pass through the signal switch circuit and a second state (or an inspection state) in which a level pattern of signals from the output pads is fixed to an inspection level pattern, according to a control signal.

Abstract: In display-OFF-control, in the case where a scan electrode is driven by using voltage levels V3, VC, and MV3 and a signal electrode is driven by using voltage levels V1 and MV, the voltage levels V1 and MV1 are alternately output in a polarity inversion cycle while fixedly outputting the voltage level VC to the scan electrode. The voltage level MV1 is set at VC when V1 is output, and the voltage level MV1 set at VC is fixedly output to the signal electrode. In display-ON-control, the voltage levels MV1 set at VC output to the signal electrode is changed to the original voltage level of MV1 when VC is fixedly output to the scan electrode. After the voltage levels V1 and MV1 are alternately output in the polarity inversion cycle, a pixel is shifted to a normal operation output period.

Abstract: An electronic apparatus which detects when a battery having a different characteristic is mixed in a plurality of batteries accommodated therein. An average voltage V1 per battery of plural batteries connected in series and an average voltage V2 per battery at a connecting point halfway of those connected batteries are detected. A difference in voltage |V1?V2| between the average voltage V1 and average voltage V2 is compared with a tolerable voltage difference ?V. If it is determined that a battery having a different characteristic is mixed, the operation of the apparatus is interrupted and an alarm is displayed or the supply of power is shut down.

Abstract: An optical network unit is associated with a multi-wavelength optical fiber communications system carrying low-power digital signals bidirectionally transmitted at a first and a second wavelength and a high-power analog video signal transmitted at a third wavelength. The unit comprises a housing having a connection for the optical fiber; and an optical filter, first and second optical units, and a beam splitter mounted in the housing. The optical filter is interposed between the fiber termination and the second optical unit, and is adapted to block light of the third wavelength but bidirectionally transmit light of the first and second wavelengths. The system is readily implemented, and any combination of the data and video services may be selected. A high level of skill is not required for changing the combination of services procured.

Abstract: An object of the invention is to provide a flat-panel display device, which has a sufficient shockproof characteristic and in which the number of component parts can be reduced so as to lower in cost. A chassis for a flat-panel display device in accordance with the invention supports a component member such as a flat-panel display element 500, and is characterized in that a main body of the chassis 100 comprises a plurality of roughly triangle openings 120 at least one side of which is adjacent and roughly parallel to a side of another opening 120 or an outer edge of the main body of the chassis 100.

Abstract: A display driver is provided including a display data RAM including a plurality of memory cells each storing display data of one pixel, a display address decoder selecting a word line of the display data RAM based on a display address, a display column address decoder selecting a column line of the display data RAM based on a display column address, read-out bit lines RB1 through RBM each coupled to a memory cell specified by a column line, a scroll display data generating circuit shifting display data output to each read-out bit line by a shift amount in line with a given scroll amount so as to generate display data, and a driving circuit driving data lines based on the display data.

Abstract: A display system is provided having an active matrix type display panel and includes first and second frame synchronization circuits and an OFF data output control circuit that output a display control signal, a scan control signal, and an OFF data output control signal based on display stopping signals for stopping image display. The data driver drives the data lines of the display panel, based on the OFF data output control signal, during a predetermined frame period that includes the second frame (the next after the first, which is the frame where the display stopping signal is input), then outputs a predetermined non-display voltage after the frame period ends. A scan driver scans scan lines of the display panel based on the scan control signal, and outputs the non-selecting voltage to all of the scan lines after the frame period ends.

Abstract: A data driver is provided that comprises: a state controller that effects transition to any of multiple states including a display ON state, a display OFF state and a sleep state, then outputs a drive control signal associated with a state of a transition destination; and a drive circuit that drive the data lines using drive power corresponding to a drive signal based on the drive control signal. When first setting data is input during the sleep state, the state controller effects transition from the sleep state to the display OFF state, and when second setting data is input during the sleep state and is followed by input of the first setting data, the state controller effects transition from the sleep state to the display OFF state, then effects transition from the display OFF state to the display ON state.

Abstract: In a display data RAM, a group of memory cells for storing grayscale data for two lines are disposed within an output pad pitch L of a display driver circuit, and at least two groups of the memory cells are arranged in a direction perpendicular to the direction in which the output pads are arranged. The grayscale data for two lines is read at a time from the display data RAM. Latch circuits latch the grayscale data for four lines based on first and second clock signals. A selector circuit selectively outputs the grayscale data for consecutive three lines from among the grayscale data latched in the latch circuit. An MLS signal conversion circuit performs MLS operation in which three lines are simultaneously selected, based on the selectively output grayscale data for three lines. A signal electrode driver circuit outputs a drive voltage to the output pads based on the MLS operation results.

Abstract: The present invention provides a display driver circuit having a simple configuration due to a decrease in the number of voltage levels and capable of preventing deterioration of contrast ratio in display drive by using MLS, an electro-optical device, and a display drive method. First to fourth bits of grayscale data corresponding to a display pattern for three lines are supplied to each ROM. The ROMs decode and output 4MLS operation results for a display pattern defined by the first to fourth bits of the grayscale data and a dummy display-pattern corresponding to the display pattern based on orthogonal functions defined by combinations of a scan pattern and a dummy scan pattern of a virtual electrode based on a field signal.

Abstract: In display-OFF-control, in the case where a scan electrode is driven by using voltage levels V3, VC, and MV3 and a signal electrode is driven by using voltage levels V1 and MV, the voltage levels V1 and MV1 are alternately output in a polarity inversion cycle while fixedly outputting the voltage level VC to the scan electrode. The voltage level MV1 is set at VC when V1 is output, and the voltage level MV1 set at VC is fixedly output to the signal electrode. In display-ON-control, the voltage levels MV1 set at VC output to the signal electrode is changed to the original voltage level of MV1 when VC is fixedly output to the scan electrode. After the voltage levels V1 and MV1 are alternately output in the polarity inversion cycle, a pixel is shifted to a normal operation output period.

Abstract: The clock may be recovered rapidly for burst mode signals that are at one of a set of different a priority known frequencies by using a single device that is similar to that of U.S. Pat. No. 5,237,290 except that the delay lines used in each of the gated oscillators are controllably selectable so that the gated oscillators are each capable of providing a clock signal at more than one frequency. Typically, the same frequency is selected for use by both of the gated oscillators at any one time. This is achieved by having each gated oscillator be made up of 1) a plurality of “internal” gated oscillators that each have different length delay lines, and 2) a selector for selecting the output of one of the internal gated oscillators that is to be used for a particular frequency. The internal gated oscillators may be made up of delay elements. The ratio of the number of delay elements in the various internal gated oscillators to each other determines their relative frequency.

Abstract: Power control for a laser is performed on at least a per-packet basis, rather than a per-pulse basis, and that end-of-life detection may similarly be performed. This is achieved by accumulating the current generated by a photodiode in response to the light signal generated by the laser, subtracting therefrom a preset threshold current which is similarly modulated in response to the data signal used to drive the laser, and comparing the resulting difference to the value prior to having begun accumulating and subtracting. The result of the comparison, which may be filtered, is used to control the driver of the laser or as an indicator, e.g., for use in end-of-life detection.

Abstract: Power control for a laser used for bust mode communication as well as end-of-life detection for the laser are performed in a combined manner, resulting in a savings in both cost and power consumption. This is achieved by employing a peak comparator which is supplied with an indication of the magnitude of a the laser signal, and supplying to the peak comparator in a time multiplexed manner with different thresholds, such as a first threshold which is used for performing power control and a second threshold which is used for performing end of life detection, on an alternative packet-by-packet basis. Thus, the first threshold is supplied for the duration of a first packet and the second threshold is used for the duration of a second packet. Additional thresholds and packets may be employed for other functions as desired by an implementor.