Patents by Inventor Yusuke Sakata
Yusuke Sakata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240149156Abstract: An object is to provide a new program with a higher level of satisfaction while increasing a player's freedom for provided content. An example content providing program determines whether or not information received from a user is similar to a predetermined character string corresponding to progress information and progresses the content in a case where it is determined that the information is similar to the predetermined character string.Type: ApplicationFiled: November 6, 2023Publication date: May 9, 2024Applicant: Square Enix Co., Ltd.Inventors: Shinpei SAKATA, Yusuke MORI
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Publication number: 20240153482Abstract: According to one or more embodiments, a non-transitory computer-readable medium including a program that, when executed, causes a server to perform functions including: converting a first text into a voice feature amount by inputting the first text into a learned conversion model, wherein the first text is in a different language from a predetermined language, the learned conversion model is pre-learned to convert a second text in the predetermined language into a voice feature amount, and synthesizing a voice from the converted voice feature amount.Type: ApplicationFiled: November 6, 2023Publication date: May 9, 2024Applicant: SQUARE ENIX CO., LTD.Inventors: Shinpei SAKATA, Yusuke MORI
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Publication number: 20240121530Abstract: A light detector is configured such that a light receiving portion having APDs and a peripheral portion are provided on a first principal surface of a p-type semiconductor substrate, and further includes a back electrode provided on a second principal surface of the semiconductor substrate and a p-type first separation portion provided between the light receiving portion and the peripheral portion. The APD has, on a first principal surface side, an n-type region and a p-epitaxial layer contacting the n-type region in a Z-direction. The peripheral portion has an n-type MISFET provided at a p-well and an n-well provided to surround entire side and bottom portions of the p-well.Type: ApplicationFiled: December 15, 2023Publication date: April 11, 2024Inventors: Tatsuya KABE, Hideyuki ARAI, Hisashi AIKAWA, Yuki SUGIURA, Akito INOUE, Mitsuyoshi MORI, Kentaro NAKANISHI, Yusuke SAKATA
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Patent number: 11889215Abstract: A light detector is configured such that a light receiving portion having APDs and a peripheral circuit portion are provided on a first principal surface of a p-type semiconductor substrate, and further includes a back electrode provided on a second principal surface of the semiconductor substrate and a p-type first separation portion provided between the light receiving portion and the peripheral circuit portion. The APD has, on a first principal surface side, an n-type region and a p-epitaxial layer contacting the n-type region in a Z-direction. The peripheral circuit portion has an n-type MISFET provided at a p-well and an n-well provided to surround side and bottom portions of the p-well.Type: GrantFiled: September 27, 2021Date of Patent: January 30, 2024Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Tatsuya Kabe, Hideyuki Arai, Hisashi Aikawa, Yuki Sugiura, Akito Inoue, Mitsuyoshi Mori, Kentaro Nakanishi, Yusuke Sakata
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Patent number: 11860033Abstract: A photodetector includes: at least one avalanche photodiode including a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type; a first transistor connected to the first semiconductor layer and including a channel of the second conductivity type that has polarity opposite to polarity of the first conductivity type; and a second transistor connected to the first semiconductor layer and including a channel of the first conductivity type.Type: GrantFiled: February 17, 2023Date of Patent: January 2, 2024Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Akito Inoue, Mitsuyoshi Mori, Yusuke Sakata, Motonori Ishii
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Publication number: 20230204415Abstract: A photodetector includes: at least one avalanche photodiode including a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type; a first transistor connected to the first semiconductor layer and including a channel of the second conductivity type that has polarity opposite to polarity of the first conductivity type; and a second transistor connected to the first semiconductor layer and including a channel of the first conductivity type.Type: ApplicationFiled: February 17, 2023Publication date: June 29, 2023Inventors: Akito INOUE, Mitsuyoshi MORI, Yusuke SAKATA, Motonori ISHII
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Publication number: 20220310684Abstract: A solid-state image sensor includes pixel cells each of which is formed in and above a semiconductor substrate and that are arranged in each of a first direction and a second direction intersecting the first direction to form a two-dimensional array. The pixel cells include a first pixel cell and a second pixel cell arranged in the second direction, and the pixel circuit of the first pixel cell and the pixel circuit of the second pixel cell are adjacent to each other in the second direction between the photodetection portion of the first pixel cell and the photodetection portion of the second pixel cell. Each of the first transistors of the first pixel cell shares a gate electrode with the first transistor of the second pixel cell that has the same function as the first transistor of the first pixel cell.Type: ApplicationFiled: June 14, 2022Publication date: September 29, 2022Inventors: Yusuke SAKATA, Masaki TAMARU, Mitsuyoshi MORI
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Publication number: 20220014701Abstract: A light detector is configured such that a light receiving portion having APDs and a peripheral circuit portion are provided on a first principal surface of a p-type semiconductor substrate, and further includes a back electrode provided on a second principal surface of the semiconductor substrate and a p-type first separation portion provided between the light receiving portion and the peripheral circuit portion. The APD has, on a first principal surface side, an n-type region and a p-epitaxial layer contacting the n-type region in a Z-direction. The peripheral circuit portion has an n-type MISFET provided at a p-well and an n-well provided to surround side and bottom portions of the p-well.Type: ApplicationFiled: September 27, 2021Publication date: January 13, 2022Inventors: Tatsuya KABE, Hideyuki ARAI, Hisashi AIKAWA, Yuki SUGIURA, Akito INOUE, Mitsuyoshi MORI, Kentaro NAKANISHI, Yusuke SAKATA
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Publication number: 20220005855Abstract: A plurality of pixel cells are provided on a semiconductor substrate and arranged in a two-dimensional array. At least one of the plurality of pixel cells includes a light receiving part, a pixel circuit, and a second transistor. The light receiving part receives an incident light to generate an electrical charge. The pixel circuit includes first transistors arranged side by side along a first direction and a charge retention part that retains the electrical charge generated by the light receiving part. The pixel circuit outputs a light receiving signal in accordance with the electrical charge generated by the light receiving part. The second transistor connects the charge retention part to a memory part that stores the electrical charge. Seen along a thickness direction of the semiconductor substrate, the second transistor is apart from the first transistors in a second direction orthogonal to the first direction.Type: ApplicationFiled: September 20, 2021Publication date: January 6, 2022Inventors: Masaki TAMARU, Shigetaka KASUGA, Yusuke SAKATA, Mitsuyoshi MORI, Shinzo KOYAMA
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Patent number: 10923614Abstract: A photodiode that multiplies a charge generated by photoelectric conversion in an avalanche region includes: a p? type semiconductor layer having interfaces; an n+ type semiconductor region located inside the p? type semiconductor layer and in contact with the interface; an n+ type semiconductor region located inside the p? type semiconductor layer and connected to the n+ type semiconductor region; and a p type semiconductor region located between the n+ type semiconductor region and the interface, wherein the n+ type semiconductor region, the n+ type semiconductor region, and the p type semiconductor region each have a higher impurity concentration than the p? type semiconductor layer, the avalanche region is a region between the n+ type semiconductor region and the p type semiconductor region inside the p? type semiconductor layer, and the n+ type semiconductor region has a smaller area than the n+ type semiconductor region in planar view.Type: GrantFiled: July 9, 2015Date of Patent: February 16, 2021Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Yusuke Sakata, Manabu Usuda, Mitsuyoshi Mori, Yutaka Hirose, Yoshihisa Kato
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Patent number: 10879301Abstract: An imaging device includes: a photoelectric converter which converts light into signal charges; a charge accumulation region which is electrically connected to the photoelectric converter, and accumulates the signal charges; a transistor having a gate electrode which is electrically connected to the charge accumulation region; and a contact plug which electrically connects the photoelectric converter to the charge accumulation region, is in direct contact with the charge accumulation region, and comprises a semiconductor material.Type: GrantFiled: January 15, 2020Date of Patent: December 29, 2020Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Yusuke Sakata, Mitsuyoshi Mori, Yutaka Hirose, Hiroshi Masuda, Hitoshi Kuriyama, Ryohei Miyagawa
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Patent number: 10767605Abstract: A heat exchanger includes: a stack formed by stacking a plurality of tubes through which gas flow; a tubular inner tank in which the stack is housed; and a tubular outer tank that is mounted on the outside of the inner tank so as to define an inner space between the outer tank and an outer peripheral surface of the inner tank. Each of both end portions of the tubes has a thickness greater than each of middle portions of the tubes. The both end portions of the tubes adjacent to each other in the stack are joined together so as to form a clearance between the middle portions of the adjacent tubes in the stack. Outer peripheries of both end portions of the stack are joined to an inner peripheral surface of the inner tank. An introduction hole for introducing a cooling medium is formed in the outer tank.Type: GrantFiled: December 20, 2016Date of Patent: September 8, 2020Assignee: TOKYO ROKI CO., LTD.Inventors: Tatsuto Yamada, Hajime Fujiki, Ryota Niimura, Yusuke Sakata, Masahiro Kanda
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Publication number: 20200152690Abstract: An imaging device includes: a photoelectric converter which converts light into signal charges; a charge accumulation region which is electrically connected to the photoelectric converter, and accumulates the signal charges; a transistor having a gate electrode which is electrically connected to the charge accumulation region; and a contact plug which electrically connects the photoelectric converter to the charge accumulation region, is in direct contact with the charge accumulation region, and comprises a semiconductor material.Type: ApplicationFiled: January 15, 2020Publication date: May 14, 2020Inventors: Yusuke SAKATA, Mitsuyoshi MORI, Yutaka HIROSE, Hiroshi MASUDA, Hitoshi KURIYAMA, Ryohei MIYAGAWA
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Patent number: 10553639Abstract: A solid-state imaging device includes: a first electrode formed above a semiconductor substrate; a photoelectric conversion film formed on the first electrode and for converting light into signal charges; a second electrode formed on the photoelectric conversion film; a charge accumulation region electrically connected to the first electrode and for accumulating the signal charges converted from the light by the photoelectric conversion film; a reset gate electrode for resetting the charge accumulation region; an amplification transistor for amplifying the signal charges accumulated in the charge accumulation region; and a contact plug in direct contact with the charge accumulation region, comprising a semiconductor material, and for electrically connecting to each other the first electrode and the charge accumulation region.Type: GrantFiled: August 22, 2018Date of Patent: February 4, 2020Assignee: Panasonic Intellectual Property Management Co., Ltd.Inventors: Yusuke Sakata, Mitsuyoshi Mori, Yutaka Hirose, Hiroshi Masuda, Hitoshi Kuriyama, Ryohei Miyagawa
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Publication number: 20190331067Abstract: A heat exchanger includes: a stack formed by stacking a plurality of tubes through which gas flow; a tubular inner tank in which the stack is housed; and a tubular outer tank that is mounted on the outside of the inner tank so as to define an inner space between the outer tank and an outer peripheral surface of the inner tank. Each of both end portions of the tubes has a thickness greater than each of middle portions of the tubes. The both end portions of the tubes adjacent to each other in the stack are joined together so as to form a clearance between the middle portions of the adjacent tubes in the stack. Outer peripheries of both end portions of the stack are joined to an inner peripheral surface of the inner tank. An introduction hole for introducing a cooling medium is formed in the outer tank.Type: ApplicationFiled: December 20, 2016Publication date: October 31, 2019Applicant: TOKYO ROKI CO., LTD.Inventors: Tatsuto Yamada, Hajime Fujiki, Ryota Niimura, Yusuke Sakata, Masahiro Kanda
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Patent number: 10192920Abstract: A solid-state imaging device includes a substrate of P type and a wiring layer. The substrate includes: a first semiconductor region disposed on a first principle surface and extending in a direction from the first principal surface toward the second principal surface; a second semiconductor region disposed between the second principal surface and the first semiconductor region and connected to the first semiconductor region; a P type semiconductor region disposed between the second principal surface and the second semiconductor regions of two pixels; and a pixel isolation region disposed inside the substrate, between the first semiconductor regions of the two pixels. The second semiconductor region and the P type semiconductor region form an avalanche multiplication region.Type: GrantFiled: March 6, 2018Date of Patent: January 29, 2019Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Yusuke Sakata, Manabu Usuda, Mitsuyoshi Mori, Yoshihisa Kato
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Publication number: 20190013349Abstract: A solid-state imaging device includes: a first electrode formed above a semiconductor substrate; a photoelectric conversion film formed on the first electrode and for converting light into signal charges; a second electrode formed on the photoelectric conversion film; a charge accumulation region electrically connected to the first electrode and for accumulating the signal charges converted from the light by the photoelectric conversion film; a reset gate electrode for resetting the charge accumulation region; an amplification transistor for amplifying the signal charges accumulated in the charge accumulation region; and a contact plug in direct contact with the charge accumulation region, comprising a semiconductor material, and for electrically connecting to each other the first electrode and the charge accumulation region.Type: ApplicationFiled: August 22, 2018Publication date: January 10, 2019Inventors: Yusuke SAKATA, Mitsuyoshi MORI, Yutaka HIROSE, Hiroshi MASUDA, Hitoshi KURIYAMA, Ryohei MIYAGAWA
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Patent number: 10084008Abstract: A solid-state imaging device includes: a first electrode formed above a semiconductor substrate; a photoelectric conversion film formed on the first electrode and for converting light into signal charges; a second electrode formed on the photoelectric conversion film; a charge accumulation region electrically connected to the first electrode and for accumulating the signal charges converted from the light by the photoelectric conversion film; a reset gate electrode for resetting the charge accumulation region; an amplification transistor for amplifying the signal charges accumulated in the charge accumulation region; and a contact plug in direct contact with the charge accumulation region, comprising a semiconductor material, and for electrically connecting to each other the first electrode and the charge accumulation region.Type: GrantFiled: August 16, 2017Date of Patent: September 25, 2018Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Yusuke Sakata, Mitsuyoshi Mori, Yutaka Hirose, Hiroshi Masuda, Hitoshi Kuriyama, Ryohei Miyagawa
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Patent number: 10077361Abstract: A surface physical property modifier composition includes (A) a wax, (B) a vinyl (co)polymer, and (C) an aliphatic hydrocarbon having a carbon number of 5 to 14. Component (A) is set to be at least one selected from the group consisting of (a1) paraffin wax, (a2) microcrystalline wax, (a3) Fischer-Tropsch wax, and (a4) polyethylene wax, and component (B) is produced from at least one of (b1) a (meth)acrylonitrile, (b2) a (meth)acrylic acid having a carbon number of 1 to 4, (b3) a hydroxyethyl (meth)acrylate or hydroxypropyl (meth)acrylate, (b4) styrene, and (b5) predetermined (meth)acrylic acid alkyl esters. Component (A) is 50 to 98 parts by mass relative to 100 parts by mass of the total of (A) and (B), and component (C) is 0.001 to 1 percent by mass relative to the total amount of (A).Type: GrantFiled: October 6, 2015Date of Patent: September 18, 2018Assignee: NOF CORPORATIONInventors: Yusuke Sakata, Tomohisa Tasaka
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Publication number: 20180197905Abstract: A solid-state imaging device includes a substrate of P type and a wiring layer. The substrate includes: a first semiconductor region disposed on a first principle surface and extending in a direction from the first principal surface toward the second principal surface; a second semiconductor region disposed between the second principal surface and the first semiconductor region and connected to the first semiconductor region; a P type semiconductor region disposed between the second principal surface and the second semiconductor regions of two pixels; and a pixel isolation region disposed inside the substrate, between the first semiconductor regions of the two pixels. The second semiconductor region and the P type semiconductor region form an avalanche multiplication region.Type: ApplicationFiled: March 6, 2018Publication date: July 12, 2018Inventors: Yusuke SAKATA, Manabu USUDA, Mitsuyoshi MORI, Yoshihisa KATO