Patents by Inventor Yusuke SEKINE
Yusuke SEKINE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8797788Abstract: A nonvolatile memory is provided. A semiconductor device (a nonvolatile memory) has a circuit configuration similar to that of a general SRAM. By providing a transistor whose off-state current is small between a stored data holding portion and a power supply line of the SRAM, leakage of electric charge from the stored data holding portion is prevented. As the transistor whose off-state current is small provided for preventing leakage of electric charge from the stored data holding portion, a transistor including an oxide semiconductor film is preferably used. Such a configuration can also be applied to a shift register, whereby a shift register with low power consumption can be obtained.Type: GrantFiled: April 18, 2012Date of Patent: August 5, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Yusuke Sekine
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Patent number: 8698219Abstract: A semiconductor device has a non-volatile memory cell including a write transistor which includes an oxide semiconductor and has small leakage current in an off state (off-state current) between a source and a drain, a read transistor including a semiconductor material different from that of the write transistor, and a capacitor. Data is written or to the memory cell by applying a potential to a node where one of a source electrode and drain electrode of the write transistor, one electrode of the capacitor, and a gate electrode of the read transistor are electrically connected to one another so that the predetermined amount of charge is held in the node. The memory window width is changed by 2% or less, before and after 1×109 times of writing.Type: GrantFiled: January 11, 2011Date of Patent: April 15, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Yusuke Sekine, Yutaka Shionoiri, Kiyoshi Kato, Shunpei Yamazaki
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Patent number: 8659957Abstract: An object is to provide a semiconductor device to reduce variation in the threshold voltages of memory cells after writing, reduce the operation voltage, or increase the storage capacity. The semiconductor device includes memory cells each including a transistor including an oxide semiconductor, a driver circuit that drives the memory cells, a potential generating circuit that generates potentials supplied to the driver circuit, and a write completion detecting circuit that detects all at once whether rewriting of data into the memory cells is completed or not. The driver circuit includes a data buffer, a writing circuit that writes one potential of the potentials into each of the memory cells as data, a reading circuit that reads the data written into the memory cells, and a verifying circuit that verifies whether the read data agrees with the data held in the data buffer or not.Type: GrantFiled: February 23, 2012Date of Patent: February 25, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Yusuke Sekine
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Semiconductor memory cell having an oxide semiconductor transistor and erasable by ultraviolet light
Patent number: 8659941Abstract: A nonvolatile memory includes a memory cell including a first transistor and a second transistor. The first transistor includes a first channel, a first gate electrode, a first source electrode, and a first drain electrode. The second transistor includes a second channel made of oxide semiconductor material, a second gate electrode, a second source electrode, and a second drain electrode. One of the second source electrode and the second drain electrode is electrically connected to the first gate electrode. Data writing in the memory cell is done by raising the potential of a node between one of the second source electrode and the second drain electrode and the first gate electrode. Data erasure in the memory cell is done by irradiating the second channel with ultraviolet light and lowering the potential of the node.Type: GrantFiled: November 22, 2010Date of Patent: February 25, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Koichiro Kamata, Yusuke Sekine -
Publication number: 20140016407Abstract: A semiconductor device with a novel structure is provided, in which the operation voltage is reduced or the storage capacity is increased by reducing variation in the threshold voltages of memory cells after writing. The semiconductor device includes a plurality of memory cells each including a transistor including an oxide semiconductor and a transistor including a material other than an oxide semiconductor, a driver circuit that drives the plurality of memory cells, and a potential generating circuit that generates a plurality of potentials supplied to the driver circuit. The driver circuit includes a data buffer, a writing circuit that writes one potential of the plurality of potentials into each of the plurality of memory cells as data, a reading circuit that reads the data written into the memory cells, and a verifying circuit that verifies whether the read data agrees with data held in the data buffer or not.Type: ApplicationFiled: September 12, 2013Publication date: January 16, 2014Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Yusuke Sekine, Kiyoshi Kato
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Patent number: 8552712Abstract: One object is to provide a method for measuring current by which minute current can be measured. A value of current flowing through an electrical element is not directly measured but is calculated from change in a potential observed in a predetermined period. The method for measuring current includes the steps of: applying a predetermined potential to a first terminal of an electrical element having the first terminal and a second terminal; measuring an amount of change in a potential of a node connected to the second terminal; and calculating, from the amount of change in the potential, a value of current flowing between the first terminal and the second terminal of the electrical element. Thus, the value of minute current can be measured.Type: GrantFiled: April 13, 2011Date of Patent: October 8, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Kiyoshi Kato, Yusuke Sekine, Yutaka Shionoiri, Kazuma Furutani
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Patent number: 8542528Abstract: A semiconductor device with a novel structure is provided, in which the operation voltage is reduced or the storage capacity is increased by reducing variation in the threshold voltages of memory cells after writing. The semiconductor device includes a plurality of memory cells each including a transistor including an oxide semiconductor and a transistor including a material other than an oxide semiconductor, a driver circuit that drives the plurality of memory cells, and a potential generating circuit that generates a plurality of potentials supplied to the driver circuit. The driver circuit includes a data buffer, a writing circuit that writes one potential of the plurality of potentials into each of the plurality of memory cells as data, a reading circuit that reads the data written into the memory cells, and a verifying circuit that verifies whether the read data agrees with data held in the data buffer or not.Type: GrantFiled: August 3, 2011Date of Patent: September 24, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Yusuke Sekine, Kiyoshi Kato
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Publication number: 20130237952Abstract: A medical device is configured to position a bag member filled with a therapeutic substance in a prescribed region of the brain. The use of this medical device involves, with a sheath inserted in the brain region, filling a therapeutic substance into a bag member through an infusion tube, followed by retracting the sheath relative to the infusion tube until the bag member protrudes forward beyond the distal end of the sheath. After this, the bag member is put indwelling in the brain region by moving an operating member relative to the infusion tube to detach the bag member from the distal end of the infusion tube.Type: ApplicationFiled: March 22, 2013Publication date: September 12, 2013Applicant: Terumo Kabushiki KaishaInventors: Toshiaki TAKAGI, Yousuke Ootani, Yusuke Sekine, Ryuusuke Takashige
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Publication number: 20120286260Abstract: A highly reliable transistor which includes an oxide semiconductor and has high field-effect mobility and in which a variation in threshold voltage is small is provided. By using the transistor, a high-performance semiconductor device, which has been difficult to realize, is provided. The transistor includes an oxide semiconductor film which contains two or more kinds, preferably three or more kinds of elements selected from indium, tin, zinc, and aluminum. The oxide semiconductor film is formed in a state where a substrate is heated. Further, oxygen is supplied to the oxide semiconductor film with an adjacent insulating film and/or by ion implantation in a manufacturing process of the transistor, so that oxygen deficiency which generates a carrier is reduced as much as possible. In addition, the oxide semiconductor film is highly purified in the manufacturing process of the transistor, so that the concentration of hydrogen is made extremely low.Type: ApplicationFiled: May 2, 2012Publication date: November 15, 2012Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Kosei NODA, Shunpei YAMAZAKI, Tatsuya HONDA, Yusuke SEKINE, Hiroyuki TOMATSU
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Publication number: 20120280715Abstract: The logic circuit includes an input terminal, an output terminal, a main logic circuit portion that is electrically connected to the input terminal and the output terminal, and a switching element electrically connected to the input terminal and the main logic circuit portion. Further, a first terminal of the switching element is electrically connected to the input terminal, a second terminal of the switching element is electrically connected to a gate of at least one transistor included in the main logic circuit portion, and the switching element is a transistor in which a leakage current in an off state per micrometer of channel width is lower than or equal to 1×10?17 A.Type: ApplicationFiled: May 1, 2012Publication date: November 8, 2012Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventor: Yusuke Sekine
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Publication number: 20120275245Abstract: A semiconductor device which is capable of high-speed writing with less power consumption and suitable for multi-leveled memory, and verifying operation. A memory cell included in the semiconductor device included a transistor formed using an oxide semiconductor and a transistor formed using a material other than an oxide semiconductor. A variation in threshold value of the memory cells is derived before data of a data buffer is written by using a writing circuit. Data in which the variation in threshold value is compensated with respect to the data of the data buffer is written to the memory cell.Type: ApplicationFiled: April 25, 2012Publication date: November 1, 2012Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Yusuke Sekine, Kiyoshi Kato
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Publication number: 20120268979Abstract: A nonvolatile memory is provided. A semiconductor device (a nonvolatile memory) has a circuit configuration similar to that of a general SRAM. By providing a transistor whose off-state current is small between a stored data holding portion and a power supply line of the SRAM, leakage of electric charge from the stored data holding portion is prevented. As the transistor whose off-state current is small provided for preventing leakage of electric charge from the stored data holding portion, a transistor including an oxide semiconductor film is preferably used. Such a configuration can also be applied to a shift register, whereby a shift register with low power consumption can be obtained.Type: ApplicationFiled: April 18, 2012Publication date: October 25, 2012Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventor: Yusuke Sekine
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Publication number: 20120230114Abstract: An object is to provide a semiconductor device to reduce variation in the threshold voltages of memory cells after writing, reduce the operation voltage, or increase the storage capacity. The semiconductor device includes memory cells each including a transistor including an oxide semiconductor, a driver circuit that drives the memory cells, a potential generating circuit that generates potentials supplied to the driver circuit, and a write completion detecting circuit that detects all at once whether rewriting of data into the memory cells is completed or not. The driver circuit includes a data buffer, a writing circuit that writes one potential of the potentials into each of the memory cells as data, a reading circuit that reads the data written into the memory cells, and a verifying circuit that verifies whether the read data agrees with the data held in the data buffer or not.Type: ApplicationFiled: February 23, 2012Publication date: September 13, 2012Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventor: Yusuke Sekine
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Publication number: 20120033505Abstract: A semiconductor device with a novel structure is provided, in which the operation voltage is reduced or the storage capacity is increased by reducing variation in the threshold voltages of memory cells after writing. The semiconductor device includes a plurality of memory cells each including a transistor including an oxide semiconductor and a transistor including a material other than an oxide semiconductor, a driver circuit that drives the plurality of memory cells, and a potential generating circuit that generates a plurality of potentials supplied to the driver circuit. The driver circuit includes a data buffer, a writing circuit that writes one potential of the plurality of potentials into each of the plurality of memory cells as data, a reading circuit that reads the data written into the memory cells, and a verifying circuit that verifies whether the read data agrees with data held in the data buffer or not.Type: ApplicationFiled: August 3, 2011Publication date: February 9, 2012Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Yusuke Sekine, Kiyoshi Kato
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Publication number: 20110278571Abstract: A semiconductor device including a first transistor and a second transistor and a capacitor which are over the first transistor is provided. A semiconductor layer of the second transistor includes an offset region. In the second transistor provided with an offset region, the off-state current of the second transistor can be reduced. Thus, a semiconductor device which can hold data for a long time can be provided.Type: ApplicationFiled: May 5, 2011Publication date: November 17, 2011Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Shunpei Yamazaki, Kiyoshi Kato, Yutaka Shionoiri, Yusuke Sekine, Kazuma Furutani, Hiromichi Godo
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Publication number: 20110254538Abstract: One object is to provide a method for measuring current by which minute current can be measured. A value of current flowing through an electrical element is not directly measured but is calculated from change in a potential observed in a predetermined period. The method for measuring current includes the steps of: applying a predetermined potential to a first terminal of an electrical element having the first terminal and a second terminal; measuring an amount of change in a potential of a node connected to the second terminal; and calculating, from the amount of change in the potential, a value of current flowing between the first terminal and the second terminal of the electrical element. Thus, the value of minute current can be measured.Type: ApplicationFiled: April 13, 2011Publication date: October 20, 2011Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Kiyoshi Kato, Yusuke Sekine, Yutaka Shionoiri, Kazuma Furutani
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Publication number: 20110175083Abstract: A semiconductor device has a non-volatile memory cell including a write transistor which includes an oxide semiconductor and has small leakage current in an off state (off-state current) between a source and a drain, a read transistor including a semiconductor material different from that of the write transistor, and a capacitor. Data is written or to the memory cell by applying a potential to a node where one of a source electrode and drain electrode of the write transistor, one electrode of the capacitor, and a gate electrode of the read transistor are electrically connected to one another so that the predetermined amount of charge is held in the node. The memory window width is changed by 2% or less, before and after 1×109 times of writing.Type: ApplicationFiled: January 11, 2011Publication date: July 21, 2011Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Yusuke Sekine, Yutaka Shionoiri, Kiyoshi Kato, Shunpei Yamazaki
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Publication number: 20110148455Abstract: An object is to provide a current measurement method which enables a minute current to be measured. To achieve this, the value of a current flowing through an electrical element is not directly measured, but is calculated from a change in potential observed in a predetermined period. The detection of a minute current can be achieved by a measurement method including the steps of applying a predetermined potential to a first terminal of an electrical element comprising the first terminal and a second terminal; measuring an amount of change in potential of a node connected to the second terminal; and calculating, from the amount of change in potential, a value of a current flowing between the first terminal and the second terminal of the electrical element.Type: ApplicationFiled: December 14, 2010Publication date: June 23, 2011Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Kiyoshi Kato, Yusuke Sekine, Yutaka Shionoiri
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Publication number: 20110122673Abstract: A nonvolatile memory includes a memory cell including a first transistor and a second transistor. The first transistor includes a first channel, a first gate electrode, a first source electrode, and a first drain electrode. The second transistor includes a second channel made of oxide semiconductor material, a second gate electrode, a second source electrode, and a second drain electrode. One of the second source electrode and the second drain electrode is electrically connected to the first gate electrode. Data writing in the memory cell is done by raising the potential of a node between one of the second source electrode and the second drain electrode and the first gate electrode. Data erasure in the memory cell is done by irradiating the second channel with ultraviolet light and lowering the potential of the node.Type: ApplicationFiled: November 22, 2010Publication date: May 26, 2011Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Koichiro KAMATA, Yusuke SEKINE