Patents by Inventor Yutaka Harada

Yutaka Harada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4709788
    Abstract: A group control apparatus for elevators includes a main station for performing a hall call registration of an elevator cage, floor remote stations, arranged in elevator halls for the respective floors of a building in which elevators are installed, for generating a hall call signal and performing a call display of the elevator cage, and a single data transmission line for coupling each of the floor remote stations to the main station and for performing serial data transmission.
    Type: Grant
    Filed: June 18, 1986
    Date of Patent: December 1, 1987
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yutaka Harada
  • Patent number: 4672244
    Abstract: A Josephson logic integrated circuit packaged on a single substrate, wherein a portion for delivering an output out of the integrated circuit is constructed of an A.C.-driven Josephson logic circuit, and a portion for driving the internal part of the integrated circuit is constructed of a D.C.-driven Josephson logic circuit.
    Type: Grant
    Filed: September 30, 1985
    Date of Patent: June 9, 1987
    Assignee: Hitachi, Ltd.
    Inventors: Yutaka Harada, Ushio Kawabe, Nobuo Kotera, Atsushi Asano
  • Patent number: 4633439
    Abstract: An A.C. powered type logic array of very high speed operations which employs Josephson devices and which can program any desired logic. The logic array comprises a first logic array which delivers AND logic signals of desired ones of input signals, and a second logic array which delivers OR logic signals of desired ones of the AND outputs. Each of the first and second logic arrays comprises a plurality of bit lines which connect a plurality of arrayed Josephson devices in series at respective rows and each of which has one end connected to a power source and the other end grounded through a resistor, and word lines which are arranged in the column direction of the Josephson device array and which are selectively coupled to the Josephson devices. Whether or not the word lines are coupled to the respective Josephson devices of the arrays, is determined by the patterns of the word lines or the patterns of the Josephson devices, thereby to program the desired logic.
    Type: Grant
    Filed: July 20, 1983
    Date of Patent: December 30, 1986
    Assignee: Hitachi, Ltd.
    Inventors: Yutaka Harada, Toshikazu Nishino
  • Patent number: 4626701
    Abstract: A rectifying circuit includes a superconductive device and a circuit which controls a magnetic field to be applied to the superconductive device in response to the phase of an A.C. signal applied to the superconductive device, the state of the superconductive device being alternately and repeatedly changed-over between a superconductive state and a nonsuperconductive state by the magnetic field so as to rectify the A.C. signal.
    Type: Grant
    Filed: February 1, 1985
    Date of Patent: December 2, 1986
    Assignee: Hitachi, Ltd.
    Inventors: Yutaka Harada, Kunio Yamashita, Nobuo Kotera, Ushio Kawabe
  • Patent number: 4518868
    Abstract: A superconductive large-scale integrated circuit chip comprises a plurality of pads, a superconductive line which short-circuits respectively adjacent pairs of the pads, and an input buffer circuit. The input buffer circuit includes a Josephson junction which is either in a superconducting state or a finite voltage state in response to a magnetic field established by current that is supplied to the superconductive line by flowing in from one of the two pads and flowing out from the other pad. The input buffer circuit wave-shapes the externally supplied signal into an amplitude-controlled signal, and the latter signal is led by a superconductive line to a circuit within the chip which requires the signal. Even when the external signal current has become abnormally great due to noise, etc., any circuit situated halfway within the chip can be prevented from malfunctioning from the magnetic flux generated by the large current.
    Type: Grant
    Filed: June 29, 1981
    Date of Patent: May 21, 1985
    Assignee: Hitachi, Ltd.
    Inventors: Yutaka Harada, Kunio Yamashita, Nobuo Kotera, Hirotoshi Tanaka
  • Patent number: 4451196
    Abstract: A transfer apparatus comprises a driving-side parallel link including first and second driving arms, a hydraulic actuator for swinging the first and second driving arms, a driven-side parallel link including first and second driven arms coupled with the first and second driving arms, respectively, suckers attached to the first and second driven arms to hold an object of transfer, a first transmission member attached to the first driving arm and having a cam follower for transmitting the swing displacements of the driving arms to the driven arms, and a second transmission member attached to the second driven arm and having a cam opening to engage the cam follower to receive the swing displacements of the driving arms through the cam follower.
    Type: Grant
    Filed: July 6, 1982
    Date of Patent: May 29, 1984
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Yutaka Harada, Kouji Takai
  • Patent number: 4084981
    Abstract: A quick hardening cement-asphalt composition used as a grout for a ballast-filled track structure comprising(a) 100 parts by weight of a cement composition prepared by adding to portland cement about 10 to 50% by weight of a mixture of a calcium aluminate-series mineral and calcium sulfate in a weight ratio of about 1:0.3 to 1:3; about 0.05 to 10% by weight of an inorganic salt, and about 0.05 to 3% by weight of at least one of an organic carboxylic acid, an organic hydroxycarboxylic acid and a salt thereof, and(b) about 30 to 400 parts by weight of an asphalt emulsion containing about 0.2 to 8% by weight of a polyoxyethylene alkyl phenyl ether, polyoxyethylene alkyl ether, polyoxyethylene alkyl ester, sorbitan alkyl ester, polyoxyethylene sorbitan alkyl ester or sucrose fatty acid ester nonionic emulsifier and about 0.05 to 2% by weight of a multivalent metal chloride, calculated as the multivalent metal ion.
    Type: Grant
    Filed: October 4, 1974
    Date of Patent: April 18, 1978
    Assignees: Japanese National Railways, Denki Kagaku Kogyo Kabushiki Kaisha, Toa Doro Kogyo Co., Ltd.
    Inventors: Yoshiro Higuchi, Yutaka Harada, Toshio Sato, Koji Nakagawa, Iwazo Kawaguchi, Yasushi Kasahara
  • Patent number: 4060425
    Abstract: This invention relates to a super rapid hardening mixture comprisingA. a super rapid hardening cement in which 11CaO.7Al.sub.2 O.sub.3. CaZ (X is a halogen atom), 3CaO.SiO.sub.2 and CaSO.sub.4 are present as indespensable components;B. at least one short range strength accelerator selected from the group consisting of a calcium aluminate material, a lime material, an amine and an ethylene glycol material and calcium sulfate hemihydrate;C. at least one emulsion selected from the group consisting of a bituminous emulsion, a rubber latex and a resin emulsion;D. from 12 to 50 weight percent of water in the total mixture.
    Type: Grant
    Filed: March 31, 1976
    Date of Patent: November 29, 1977
    Assignees: Japanese National Railways, Onoda Cement Company Limited, Nichireki Chemical Industry Company Limited
    Inventors: Yutaka Harada, Noriyuki Itai, Hiroshi Ucikawa, Hajime Kato, Katutoshi Sato, Akira Itoh