Patents by Inventor Yutaka Kaneda

Yutaka Kaneda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6800816
    Abstract: A method of manufacturing a wiring circuit board having bumps is disclosed in which a stable bump connection is possible, and complex operations such as plating pre-treatment are unnecessary. Bumps having a surface roughness on the tip face thereof of 0.2 to 20 &mgr;m are formed by forming an etching mask for bump formation on bump formation surface of a metal foil which has a thickness (t1+t2) which is the sum of a thickness t1 of a wiring circuit and a height t2 of bumps to be formed on wiring circuit and which has a surface roughness of the bump formation surface thereof of 0.2 to 20 &mgr;m, and half etching the metal foil from the side of the etching mask for bump formation to a depth corresponding to the desired bump height t2.
    Type: Grant
    Filed: September 14, 2001
    Date of Patent: October 5, 2004
    Assignee: Sony Chemicals Corp
    Inventor: Yutaka Kaneda
  • Publication number: 20040188139
    Abstract: A method of manufacturing a wiring circuit board having bumps is disclosed in which a stable bump connection is possible, and complex operations such as plating pre-treatment are unnecessary. Bumps having a surface roughness on the tip face thereof of 0.2 to 20 &mgr;m are formed by forming an etching mask for bump formation on bump formation surface of a metal foil which has a thickness (t1+t2) which is the sum of a thickness t1 of a wiring circuit and a height t2 of bumps to be formed on wiring circuit and which has a surface roughness of the bump formation surface thereof of 0.2 to 20 &mgr;m, and half etching the metal foil from the side of the etching mask for bump formation to a depth corresponding to the desired bump height t2.
    Type: Application
    Filed: April 7, 2004
    Publication date: September 30, 2004
    Applicant: Sony Chemicals Corp.
    Inventor: Yutaka Kaneda
  • Publication number: 20030201242
    Abstract: Wiring circuit boards with bumps can be manufactured such that stable bump connections are possible and plating pre-treatments or other difficult operations are rendered unnecessary. By utilizing a technique whereby a bump-formation etching mask 7 is formed on a bump-forming surface 3a of a metal foil 3 which has a thickness that is the sum of the thickness t1 of the wiring circuit 1 and the height t2 of the bumps 2 which are to be formed on the wiring circuit 1 (t1+t2), and then the bumps 2 are formed by half-etching the metal foil 3 to a depth corresponding to the desired bump height t2 from the bump-formation etching mask 7 side, wiring circuit boards with bumps can be manufactured such that stable bump connections are possible and plating pre-treatments or other complex processes are rendered unnecessary.
    Type: Application
    Filed: April 1, 2003
    Publication date: October 30, 2003
    Applicant: Sony Chemicals Corporation
    Inventors: Yutaka Kaneda, Keiichi Naito, Toshihiro Shinohara
  • Publication number: 20030116350
    Abstract: A process for manufacturing a flexible wiring board with easy handling at reduced production costs comprises the steps of forming a first wiring pattern and a guide pattern around the outer periphery of the first wiring pattern on a copper foil, and forming an insulating film on the first wiring pattern and guide pattern.
    Type: Application
    Filed: December 21, 2001
    Publication date: June 26, 2003
    Applicant: SONY CHEMICALS CORP.
    Inventor: Yutaka Kaneda
  • Patent number: 6562250
    Abstract: Wiring circuit boards with bumps can be manufactured such that stable bump connections are possible and plating pre-treatments or other difficult operations are rendered unnecessary. By utilizing a technique whereby a bump-formation etching mask 7 is formed on a bump-forming surface 3a of a metal foil 3 which has a thickness that is the sum of the thickness t1 of the wiring circuit 1 and the height t2 of the bumps 2 which are to be formed on the wiring circuit 1 (t1+t2), and then the bumps 2 are formed by half-etching the metal foil 3 to a depth corresponding to the desired bump height t2 from the bump-formation etching mask 7 side, wiring circuit boards with bumps can be manufactured such that stable bump connections are possible and plating pre-treatments or other complex processes are rendered unnecessary.
    Type: Grant
    Filed: October 27, 2000
    Date of Patent: May 13, 2003
    Assignee: Sony Chemicals Corporation
    Inventors: Yutaka Kaneda, Keiichi Naito, Toshihiro Shinohara
  • Patent number: 6553122
    Abstract: Even if received signals are highly cross-correlated, echoes can be effectively cancelled and no psychoacoustical problems arise. A received signal xi(k) (where i=1, 2, . . . , N) and an additive signal ai(k) are added together, and the added output is used to drive a speaker i and input into an echo cancellation filter 405i. The received signal xi(k) and the additive signal ai(k) are input into adaptive filters 401i and 402i, respectively. The difference between the sum of the outputs from all the filters 401i and all the filters 402i and an echo ym(k) is detected as an error em(k). The coefficients of all the filters 401i and 402i are updated to reduce the error em(k). When the error em(k) is made sufficiently small, the coefficients of the filters 402i are transferred to the filters 405i. The sum of the outputs from all the filters 405i is detected as an echo replica, and the difference between the echo replica and the echo ym(k) is output.
    Type: Grant
    Filed: March 2, 1999
    Date of Patent: April 22, 2003
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Suehiro Shimauchi, Yoichi Haneda, Shoji Makino, Yutaka Kaneda
  • Publication number: 20030034173
    Abstract: An object of the present invention is to manufacture a bump-attached wiring circuit board with which stable bump connections are possible, and there is no need for bothersome operations such as plating pretreatments. A bump formation etching mask 7 is formed on the bump formation side 3a of a metal foil 3 having a thickness (t1+t2) equal to the sum of the thickness t1 of a wiring circuit 1 and the height t2 of the bumps 2 to be formed on a wiring circuit 1, the bumps 2 are formed by half-etching the metal foil 3 from the bump formation etching mask 7 side down to a depth corresponding to a predetermined bump height t2, and a metal thin film layer 10 composed of a different metal from the metal foil 3 is formed on the bump formation side of the metal foil 3, thereby providing a bump-attached wiring circuit board with which stable bump connections are possible, and there is no need for bothersome operations such as plating pretreatments.
    Type: Application
    Filed: October 11, 2002
    Publication date: February 20, 2003
    Applicant: Sony Chemicals Corp.
    Inventors: Yutaka Kaneda, Keiichi Naito, Soichiro Kishimoto, Toshihiro Shinohara
  • Patent number: 6518510
    Abstract: A bump formation etching mask is formed on the bump formation side of a metal foil having a thickness (t1+t2) equal to the sum of the thickness t1 of a wiring circuit and the height t2 of the bumps to be formed on a wiring circuit. The bumps are formed by half-etching the metal foil from the bump formation etching mask side down to a depth corresponding to a predetermined bump height t2. A metal thin film layer formed of a different metal from the metal foil is formed on the bump formation side of the metal foil, thereby providing a bump-attached wiring circuit board with which stable bump connections are possible, and there is no need for bothersome operations, such as plating pretreatments.
    Type: Grant
    Filed: July 2, 2001
    Date of Patent: February 11, 2003
    Assignee: Sony Chemicals Corp.
    Inventors: Yutaka Kaneda, Keiichi Naito, Soichiro Kishimoto, Toshihiro Shinohara
  • Publication number: 20020079134
    Abstract: In one embodiment, the present invention provides a process for manufacturing a multilayer flexible wiring board, which allows individual layers of wiring boards to be precisely positioned and to be readily stacked. A mask for exposure is prepared in which a plurality of pattern holes corresponding to individual layers of wiring boards of a multilayer flexible wiring board are arranged in the direction perpendicular to the transporting direction P of substrate. This mask for exposure is used to form a plurality of wiring patterns corresponding to individual layers of wiring boards of a multilayer flexible wiring board on the same sheet-like substrate.
    Type: Application
    Filed: December 20, 2001
    Publication date: June 27, 2002
    Inventor: Yutaka Kaneda
  • Publication number: 20020038721
    Abstract: A method of manufacturing a wiring circuit board having bumps is disclosed in which a stable bump connection is possible, and complex operations such as plating pre-treatment are unnecessary. Bumps having a surface roughness on the tip face thereof of 0.2 to 20 &mgr;m are formed by forming an etching mask for bump formation on bump formation surface of a metal foil which has a thickness (t1+t2) which is the sum of a thickness t1 of a wiring circuit and a height t2 of bumps to be formed on wiring circuit and which has a surface roughness of the bump formation surface thereof of 0.2 to 20 &mgr;m, and half etching the metal foil from the side of the etching mask for bump formation to a depth corresponding to the desired bump height t2.
    Type: Application
    Filed: September 14, 2001
    Publication date: April 4, 2002
    Applicant: Sony Chemicals Corp.
    Inventor: Yutaka Kaneda
  • Publication number: 20020005292
    Abstract: An object of the present invention is to manufacture a bump-attached wiring circuit board with which stable bump connections are possible, and there is no need for bothersome operations such as plating pretreatments. A bump formation etching mask 7 is formed on the bump formation side 3a of a metal foil 3 having a thickness (t1+t2) equal to the sum of the thickness t1 of a wiring circuit 1 and the height t2 of the bumps 2 to be formed on a wiring circuit 1, the bumps 2 are formed by half-etching the metal foil 3 from the bump formation etching mask 7 side down to a depth corresponding to a predetermined bump height t2, and a metal thin film layer 10 composed of a different metal from the metal foil 3 is formed on the bump formation side of the metal foil 3, thereby providing a bump-attached wiring circuit board with which stable bump connections are possible, and there is no need for bothersome operations such as plating pretreatments.
    Type: Application
    Filed: July 2, 2001
    Publication date: January 17, 2002
    Applicant: SONY CHEMICALS CORP.
    Inventors: Yutaka Kaneda, Keiichi Naito, Soichiro Kishimoto, Toshihiro Shinohara
  • Publication number: 20010050434
    Abstract: An object of the present invention is to provide a simple process for manufacturing a flexible printed wiring board having fine metal bumps.
    Type: Application
    Filed: July 23, 2001
    Publication date: December 13, 2001
    Applicant: Sony Chemicals Corp.
    Inventors: Yutaka Kaneda, Akira Tsutsumi, Hiroyuki Hishinuma
  • Patent number: 6312614
    Abstract: A semiconductor element mounting interposer is produced by (A) forming a conducting circuit that comprises motherboard connecting electrodes 2 and plated leads 3 on an insulating base film 1; (B) forming a patterning resin layer 5 over the conducting circuit 4; (C) etching patterning resin layer 5 so as to expose the motherboard connecting electrodes 2 and plated leads 3; (D) masking plated leads 3 with an electroplating resist layer 6; (E) depositing an electroplated metal layer 7 over the exposed motherboard connecting electrodes 2; (F) removing the electroplating resist layer 6; (G) removing the exposed plated leads 3 through etching; and (H) where the patterning resin layer 5 is a polyimide precursor layer, bringing about complete imidation of the polyimide precursor layer.
    Type: Grant
    Filed: May 25, 2000
    Date of Patent: November 6, 2001
    Assignee: Sony Chemicals Corporation
    Inventors: Yoshio Arimitsu, Yutaka Kaneda
  • Patent number: 6294316
    Abstract: An object of the present invention is to provide a simple process for manufacturing a flexible printed wiring board having fine metal bumps. A resin coating 21 and a resist film 24 are formed in this order on the surface of a metal film 11 and on the surface of each metal bump 16 formed on the metal film 11, and a pressure is applied on the surface to depress the resist film 24 on the metal bump 16, followed by etching. As the surface of the resin coating 21 is partially exposed at the depressed portion of the resist film 24, etching of the resin coating 21 proceeds from that portion to bulge the surface of the metal bump 16 from the resin coating 21.
    Type: Grant
    Filed: January 5, 2000
    Date of Patent: September 25, 2001
    Assignee: Sony Chemicals Corp.
    Inventors: Yutaka Kaneda, Akira Tsutsumi, Hiroyuki Hishinuma
  • Patent number: 5774562
    Abstract: In a method and an apparatus for dereverberation provided speech from speaker is received by a first and second channel microphones which are disposed at different locations, and is input to a first and a second channel reverberant speech input terminal. Input signal in each channel is processed by an inverse filter processor, and a dereverberation evaluation part evaluates dereverberation performance on the basis of an output signal from the inverse filter processor and the input signals of respective channels. Subsequently, filter coefficients in the inverse filter processor are determined and updated in accordance with the evaluation so that a result of evaluation is brought closer to an optimum. By repeating this process, an optimum dereverberation is always enabled in a manner following a variation in an in-room impulse response.
    Type: Grant
    Filed: March 24, 1997
    Date of Patent: June 30, 1998
    Assignee: Nippon Telegraph and Telephone Corp.
    Inventors: Kenichi Furuya, Yutaka Kaneda
  • Patent number: 5602765
    Abstract: In an adaptive estimation of an acoustic transfer function of an unknown system, a forward linear prediction coefficient vector a(k) of an input signal x(k), the sum of forward a posteriori prediction-error squares F(k), a backward linear prediction coefficient vector b(k) of the input signal x(k) and the sum of backward a posteriori prediction-error squares B(k) are computed. Letting a step size and a pre-filter deriving coefficient vector be represented by .mu.
    Type: Grant
    Filed: July 21, 1994
    Date of Patent: February 11, 1997
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Masashi Tanaka, Yutaka Kaneda, Shoji Makino, Yoichi Haneda, Junji Kojima
  • Patent number: 5539731
    Abstract: In an echo cancelling method of a p-order fast projection algorithm which subtracts an estimated echo signal y(k) from a microphone output signal u(k) to obtain an error signal e(k), adaptively calculates a pre-filter coefficient .beta.(k) from the auto-correlation of a received speech signal x(k) and the error signal, generating an intermediate variable z(k) updated by a coefficient s(k) obtained by smoothing the pre-filter coefficient, convolutes the received speech signal x(k) and the intermediate variable z(k), calculates the inner product of the auto-correlation of the received speech signal and the smoothed pre-filter coefficient s(k) and adding the inner product and the convoluted output to obtain the estimated echo signal, the magnitudes of the received speech signal x(k) and the error signal e(k) are compared and when the result of comparison satisfies a predetermined condition, a reset signal is generated to set the pre-filter coefficient .beta.
    Type: Grant
    Filed: February 9, 1995
    Date of Patent: July 23, 1996
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Yoichi Haneda, Shoji Makino, Masashi Tanaka, Yutaka Kaneda
  • Patent number: 5408530
    Abstract: A received signal vector x(n), a coefficient error covariance matrix P(n) from a memory part 12 and a forgetting factor .nu. from a memory part 13 are provided to a gain calculating part 14 to obtain a gain vector k(n). The thus obtained gain vector k(n) and an error e(n) between an echo and an echo replica are multiplied in a multiplying part 16. The multiplied output and a filter coefficient h(n) from a memory part 18 are added together to update the latter. The thus updated filter coefficient is used as the filter coefficient of an estimated echo path (an FIR filter, for example). The coefficient error covariance matrix P(n), the gain vector k(n), the received signal vector x(n) and the forgetting factor .nu.
    Type: Grant
    Filed: September 28, 1993
    Date of Patent: April 18, 1995
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Shoji Makino, Yutaka Kaneda
  • Patent number: 5208864
    Abstract: According to a method of detecting an acoustic signal, first and second sound receiving units are located at substantially the same position and are used to output signals having different target signal power to noise power ratios (S/N ratios). When a difference between the powers of the signals output from the first and second sound receiving units or a ratio of the power of the signal from the first sound receiving unit to that from the second sound receiving unit in a given period falls within a predetermined range, reception of the target signal within the given period is discriminated. The first sound receiving unit is an adaptive microphone array capable of controlling directivity characteristics in correspondence with a noise position.
    Type: Grant
    Filed: March 8, 1990
    Date of Patent: May 4, 1993
    Assignee: Nippon Telegraph & Telephone Corporation
    Inventor: Yutaka Kaneda
  • Patent number: 5187692
    Abstract: A plurality of acoustic transfer functions for a plurality of sets of different positions of a loudspeaker and a microphone in an acoustic system are measured by an acoustic transfer function measuring part. The plurality of measured acoustic transfer functions are used to estimate poles of the acoustic system by a pole estimation part, and a fixed AR filter is provided with the estimated poles as fixed values. A variable MA filter is connected in series to the fixed AR filter and the acoustic transfer function of the acoustic system is simulated by the two filters. The filter coefficients of the variable MA filter are modified with a change in the acoustic transfer function of the acoustic system.
    Type: Grant
    Filed: March 20, 1992
    Date of Patent: February 16, 1993
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Yoichi Haneda, Shoji Makino, Yutaka Kaneda