Patents by Inventor Yutaka Koshino

Yutaka Koshino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5637894
    Abstract: A charge coupled device, together with a method for manufacturing the device, is provided which can eliminate a conventional problem, that is, the remaining of a light-receiving film at a great step area and a consequent lowering of a sensitivity resulting from the shutting-off of a portion of incident light. In the charge coupled device, insulating areas are formed in substantially strip-like array on a silicon substrate. Respective transfer electrodes are formed on a gate insulating film on a semiconductor substrate with an insulating areas interposed. The respective phase transfer electrodes are electrically separated by the insulating area. By doing so, the respective phase transfer electrodes can be formed on the same plane without leaving a greater step. This can achieve a thinned light shielding film.
    Type: Grant
    Filed: October 18, 1995
    Date of Patent: June 10, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masako Hori, Masaaki Ogawa, Hidenori Shibata, Yoshiyuki Shioyama, Yutaka Koshino
  • Patent number: 5229323
    Abstract: A method for manufacturing a semiconductor device with a Schottky electrode includes the steps of subjecting the surface of a GaAs substrate to a sputtering etching process in a sputtering processing chamber of a sputtering device; and depositing Schottky electrode material by sputtering on the surface of the substrate to form a Schottky electrode in the processing chamber without exposing the substrate to the atmosphere.
    Type: Grant
    Filed: March 9, 1992
    Date of Patent: July 20, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kizashi Shimada, Tatsuo Akiyama, Yutaka Koshino
  • Patent number: 5126817
    Abstract: A dielectrically isolated structure for use in an SOI-type semiconductor device according to the present invention comprises a substrate having an element-forming region formed therein on a first insulating film, the region being made of a first material, at least one trench formed in the element-forming region and extending to the first insulating film, second insulating films formed on side walls of the trench, and a film made of a second material, and embedded in only an upper portion of the trench such that a bottom portion of the trench is hollow.
    Type: Grant
    Filed: October 12, 1990
    Date of Patent: June 30, 1992
    Assignees: Kabushiki Kaisha Toshiba, Tokuda Seisakusho Co., Ltd.
    Inventors: Yoshiro Baba, Yutaka Koshino, Akihiko Osawa, Kenji Yamawaki
  • Patent number: 5086332
    Abstract: A planar semiconductor device having a high breakdown voltage includes a semiconductor layer of a first conductivity type and a first semiconductor region of a second conductivity type selectively formed, together with the semiconductor layer, in the surface of the semiconductor layer forming a pn junction. The first semiconductor region is formed to have an impurity concentration higher than that of the semiconductor layer and therefore a resistivity higher than that of the semiconductor layer. A second semiconductor region of the second conductivity type having an impurity concentration lower than that of the first semiconductor region, is formed around and in contact with the first semiconductor region and together with the semiconductor layer constitutes a pn junction. A high resistance film is formed at least over the first semiconductor region and the second semiconductor region. A voltage is applied across the high resistance film to create a uniform electric field in the high resistance film.
    Type: Grant
    Filed: September 27, 1989
    Date of Patent: February 4, 1992
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akio Nakagawa, Kiminori Watanabe, Yutaka Koshino, Yoshihiro Yamaguchi, Yoshiro Baba
  • Patent number: 5084408
    Abstract: For controlling unwanted production of crystal defects from corners of isolated regions in a complete dielectric isolation structure, after at least one trench or groove is provided through a mask of an insulating film in a semiconductor substrate adhered to an insulating film of a base substrate, the mask is side-etched and the insulating film of the base substrate is selectively etched at the same time to expose corners of the semiconductor substrate. The exposed corners of the semiconductor substrate is then subjected to isotropic etching to remove a pointed portion therefrom. Thereafter, side surfaces of the semiconductor substrate exposed within the trench is oxidized to provide an insulating film for dielectric isolation which has rounded corners.
    Type: Grant
    Filed: October 15, 1990
    Date of Patent: January 28, 1992
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshiro Baba, Yutaka Koshino, Akihiko Osawa, Satoshi Yanagiya
  • Patent number: 5049954
    Abstract: A Schottky gate electrode structure of a GaAs field effect semiconductor device comprises a Ti film having a thickness of 2 nm to 25 nm and provided adherently on a GaAs substrate including source and drain regions, and a refractory electrode film provided on the Ti film and formed of a material selected from W, Mo, Cr, Ta, Nb, V, Hf, Zr, nitrides of these metals, silicides of these metals, carbides of these metals, Ti-W alloys, WSixNy, TiNx, and TiSix. Adhesion of the refractory electrode film to the GaAs substrate is increased, and heat resisting properties of Schottky characteristics are improved according to the thin Ti film.
    Type: Grant
    Filed: December 5, 1989
    Date of Patent: September 17, 1991
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kizashi Shimada, Tatsuo Akiyama, Yutaka Koshino
  • Patent number: 5031021
    Abstract: There is disclosed a power transistor comprising a semiconductor substrate having a PN junction exposed on a major surface of the semiconductor substrate, and a semiinsulative polysilicon film formed on the major surface, the polysilicon film covering the PN junction, the polysilicon film containing at least one of carbon, oxygen, and nitrogen, and the polysilicon film having a thickness of about 3000 .ANG..
    Type: Grant
    Filed: September 11, 1986
    Date of Patent: July 9, 1991
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshiro Baba, Kazuo Tsuru, Tatsuo Akiyama, Yutaka Koshino
  • Patent number: 5029324
    Abstract: A semiconductor device has a semiconductor region, an electrode layer formed over the semiconductor region, and a protection layer formed to cover the semiconductor region and the electrode layer. In the semiconductor device, the protection layer is a semiconductor protection layer. Part of the semiconductive protection layer is formed thin so as to have a low resistance, permitting a corresponding portion of the electrode layer to be connected to an external bonding wire.
    Type: Grant
    Filed: April 16, 1990
    Date of Patent: July 2, 1991
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akihiko Osawa, Yutaka Koshino, Yoshiro Baba
  • Patent number: 4984052
    Abstract: A bonded substrate comprises a first semiconductor substrate in which a plurality of semiconductor elements are formed, a second semiconductor substrate adhered to the first semiconductor substrate so as to support it by means of an insulating layer interposed therebetween, a first semi-insulating polysilicon layer interposed between the first semiconductor substrate and the insulating layer, and a second semi-insulating polysilicon layer interposed between the insulating layer and the second semiconductor substrate. The semi-insulating polysilicon layers serve to reduce the voltage applied to the insulating layer and to prevent the insulating layer from being etched.
    Type: Grant
    Filed: October 10, 1989
    Date of Patent: January 8, 1991
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yutaka Koshino, Yoshiro Baba, Akihiko Osawa, Satoshi Yanagiya
  • Patent number: 4968932
    Abstract: An evaluation method for a semiconductor device includes the steps of applying a reverse bias voltage between an N-type substrate formed in a surface of the semiconductor device and a P-type region formed in a surface of the N-type substrate to form a depletion layer along the junction therebetween, scanning the surface of the semiconductor device is one direction with a light beam to cause an optical beam induced current to be flow across the junction, and measuring the OBIC intensity profile on a scanning line extending across the depletion layer in the surfaces of the N-type substrate and P-type region. In the method, the light beam has a wavelength whose penetration length is smaller than the depth or thickness of the P-type region, the OBIC intensity profile is integrated over a range corresponding to the depletion layer, and the integrated value is normalized by the reverse bias voltage to determine the surface potential distribution of the semiconductor device.
    Type: Grant
    Filed: September 30, 1988
    Date of Patent: November 6, 1990
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshiro Baba, Yutaka Koshino, Seiji Yasuda
  • Patent number: 4780426
    Abstract: A first silicon oxide film is formed on the major surface of an n-type silicon substrate. A silicon nitride film is formed on the first silicon oxide film. The first silicon oxide film and the silicon nitride film are selectively etched to form an opening. Boron ions are implanted into the silicon substrate using the first silicon oxide film and the silicon nitride film as a mask. A second silicon oxide film is formed on the silicon substrate exposed by the opening. Gallium ions are implanted into the second silicon oxide film using the silicon nitride film as a mask. Boron and gallium ions are simultaneously diffused in the silicon substrate. In this case, a diffusion rate of gallium in the silicon substrate is higher than that of boron in the silicon substrate, and the diffusion rate of gallium in the silicon oxide film is higher than that in the silicon substrate. Therefore, a p-type second layer is formed in the substrate to surround a p.sup.+ -type first layer in a self-aligned manner.
    Type: Grant
    Filed: September 24, 1987
    Date of Patent: October 25, 1988
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yutaka Koshino, Yoshiro Baba, Jiro Ohshima
  • Patent number: 4729966
    Abstract: A first insulative film is formed with predetermined height and thickness in a loop shape on the surface of the Schottky-junction semiconductor substrate. A gate electrode metal film is formed with a predetermined height and thickness in a loop shape on the surface of the substrate along the inner surface of the first insulative film. A second insulative film is formed with a predetermined height and thickness in a loop shape on the surface of the substrate along the inner surface of the metal film. A channel consisting of a low concentration impurity layer, is formed in a loop shape inside the substrate directly under the metal film and the first and second insulative films. The source region consists of a high-concentration impurity layer formed such that it surrounds the channel positioned inside the substrate on the outside of the first insulative film.
    Type: Grant
    Filed: March 26, 1986
    Date of Patent: March 8, 1988
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yutaka Koshino, Tatsuo Akiyama, Shunichi Hiraki
  • Patent number: 4710794
    Abstract: Disclosed is a composite semiconductor device, comprising a composite substrate consisting of first and second semiconductor substrates, one surface of each of which is mirror-polished, so that the mirror-polished surfaces are bonded together.
    Type: Grant
    Filed: February 12, 1986
    Date of Patent: December 1, 1987
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yutaka Koshino, Tatsuo Akiyama, Yoshiro Baba
  • Patent number: 4700455
    Abstract: A method of manufacturing a semiconductor device wherein an insulating film of silicon dioxide is provided on the sidewalls of a gate electrode. This silicon dioxide film is used to define the length of the gate region during formation of the source and drain regions by ion implantation, and to accurately position the gate electrode relative to the source and drain regions.
    Type: Grant
    Filed: October 30, 1985
    Date of Patent: October 20, 1987
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kizashi Shimada, Tatsuo Akiyama, Yutaka Koshino
  • Patent number: 4585489
    Abstract: A semiconductor device and a method of manufacturing the same are disclosed wherein a semi-insulating film having a high trap density is formed on a semiconductor substrate so as to prevent charges from remaining in the semi-insulating film and to prevent a change in carrier density at the substrate surface upon irradiation thereof with radiation. The lifetime of minority carriers can be easily controlled without decreasing the junction breakdown voltages.
    Type: Grant
    Filed: September 7, 1984
    Date of Patent: April 29, 1986
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shun-ichi Hiraki, Kazuo Tsuru, Yoshikazu Usuki, Yutaka Koshino
  • Patent number: 4566174
    Abstract: A method of manufacturing a semiconductor device wherein a pair of grooves having different depths are formed in a surface of a semiconductor substrate, an epitaxial layer of one conductivity type is grown to a depth enough to fill a shallower one of the grooves, and an epitaxial layer of the opposite conductivity type is further grown to a depth enough to fill a deeper one of the grooves, followed by the step of etching the entire surface to expose the surface of said semiconductor substrate and to leave in each groove an epitaxial layer of mutually different conductivity type and having the same depth and width. A semiconductor device as manufactured by the above method.
    Type: Grant
    Filed: October 26, 1983
    Date of Patent: January 28, 1986
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Seiji Yasuda, Yutaka Koshino, Toshio Yonezawa
  • Patent number: 4560642
    Abstract: A method of manufacturing a semiconductor device which comprises the step of applying a silicon carbide film having a prescribed perforated pattern as a masking film selectively to etch a silicon dioxide film or diffuse an impurity into a substrate.
    Type: Grant
    Filed: July 19, 1984
    Date of Patent: December 24, 1985
    Assignee: Toyko Shibaura Electric Co., Ltd.
    Inventors: Toshio Yonezawa, Takashi Ajima, Shunichi Hiraki, Yutaka Koshino, Yoshitami Oka
  • Patent number: 4542400
    Abstract: A semiconductor device comprising a substrate means, a semiconductor layer of an N conductivity type formed on the substrate means, a first semiconductor region of a P conductivity type formed in the semiconductor layer and having its exposed major surface, a second semiconductor region of the N conductivity type formed in the first semiconductor region and having its exposed major surface, a first insulation layer means having a positive polarity type of charge and formed on the N semiconductor layer, and a second insulation layer means having a negative polarity type of charge and formed on the P semiconductor region.
    Type: Grant
    Filed: September 1, 1983
    Date of Patent: September 17, 1985
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Shunichi Hiraki, Kuniaki Kumamaru, Yutaka Koshino, Toshio Yonezawa
  • Patent number: 4532004
    Abstract: A method of manufacturing a GaAs FET is disclosed. In this manufacturing method, a protection film is formed on a GaAs substrate and a dummy gate electrode is formed thereon. A channel length setting film is isotropically formed on the dummy gate electrode to have a constant thickness. Then, an impurity is ion-implanted in the channel length setting film. Thereafter, the channel length setting film is removed. An etching preventive film is anisotropically formed along a substantially vertical direction with respect to the GaAs substrate. The dummy gate electrode is etched using the etching preventive film as a mask so as to form a first opening in the etching preventive film. Then, a second opening is formed in the region of the protection film corresponding to the region in which the dummy gate electrode was present. A gate electrode is formed to be in contact with the GaAs substrate through the first and second openings.
    Type: Grant
    Filed: July 31, 1984
    Date of Patent: July 30, 1985
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo Akiyama, Yutaka Koshino, Shunichi Hiraki
  • Patent number: 4515642
    Abstract: In a method of producing a semiconductor device, an alumina layer is formed directly on a principal surface of a silicon substrate; aluminum and silicon are ion-implanted through the alumina layer into said substrate; and the substrate is thereafter annealed. The ion-implanted silicon yields better crystalline structure and increases the solid solubility limit of aluminum.
    Type: Grant
    Filed: August 22, 1983
    Date of Patent: May 7, 1985
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Takashi Ajima, Jiro Ohshima, Yutaka Koshino