Patents by Inventor Yutaka Ota

Yutaka Ota has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140239772
    Abstract: In an electronic component, when L0 is a dimension of an electronic component body in a first direction, L1 is a distance between a first outer electrode and a second outer electrode on a first surface in the first direction, and L2 is a dimension of each of the first and second outer electrodes on the first surface in the first direction, 0%<L1/L0<10% and 30%<L2/L0<50% are satisfied.
    Type: Application
    Filed: February 6, 2014
    Publication date: August 28, 2014
    Applicant: MURATA MANUFACTURING CO., LTD.
    Inventors: Yutaka OTA, Masato KIMURA, Kota ZENZAI
  • Publication number: 20130294009
    Abstract: In an electronic component, a body includes top and bottom surfaces, first and second end surfaces, and first and second lateral surfaces. A first outer electrode partially extends over the bottom surface and the first end surface without being disposed on the top surface, the second end surface, and both the lateral surfaces. A second outer electrode partially extends over the bottom surface and the second end surface without being disposed on the top surface, the first end surface, and both the lateral surfaces. An area of a first end surface portion of the first outer electrode disposed on the first end surface and area of a second end surface portion of the second outer electrode disposed on the second end surface are in a range of about 6.6% to about 35.0% of area of the first and second end surfaces, respectively.
    Type: Application
    Filed: April 19, 2013
    Publication date: November 7, 2013
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Syunsuke TAKEUCHI, Yutaka OTA
  • Patent number: 8476641
    Abstract: A switching resistance RAM that is highly integrated as well as reduced in a read-out time is realized. There is formed an NPN type bipolar transistor BT composed of a collector layer made of an N-well 11, a base layer made of a P+ type Si layer 12A formed in a surface of the N-well 11, and an emitter layer made of an N+ type Si layer 15 formed in a surface of the P+ type Si layer 12A. Also, there are formed a word line WL0 electrically connected to the N+ type Si layer 15 and bit lines BL1-BL4 intersecting with the word line WL0. Also, there are formed a plurality of switching layers 14 formed on a surface of the P+ type Si layer 12A, each being electrically connected to corresponding each of the bit lines and switching between an ON state and an OFF state and an electric potential fixing line 19A to fix the P+ type Si layer 12A at a predetermined electric potential.
    Type: Grant
    Filed: September 8, 2008
    Date of Patent: July 2, 2013
    Assignee: National University Corporation Tokyo University of Agriculture and Technology
    Inventors: Yoshiyuki Suda, Yutaka Ota
  • Publication number: 20130069961
    Abstract: A projector of an embodiment is provided with: an input line memory which holds an input image signal corresponding to one line; an image processor which generates an intermediate image signal correction-processed according to distortion of a projection lens, using the input image signal transferred from the input line memory; an output line memory which holds the intermediate image signal corresponding to one line; and an LCOS which guides light radiated from a light source to the projection lens in accordance with the intermediate image signal. The image processor is provided with an input supplementation buffer which stores the input image signals of a plurality of lines, an input data buffer which stores input image signals required to generate the intermediate image signal corresponding to one line, and a number-of-supplementary-lines calculator which calculates the number of supplementary lines of the input image signals.
    Type: Application
    Filed: March 15, 2012
    Publication date: March 21, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yutaka Ota, Ryuji Hada
  • Patent number: 8266596
    Abstract: Every time an assignment statement is executed during performing a simulation according to a second variable memory system, it is determined whether a value interpreted to have the same meaning is assigned to the assignment statement in the simulation according to a first variable memory system and in the simulation according to the second variable memory system. When the value interpreted to have the same meaning is not assigned, the value assigned according to the second variable memory system is overwritten by an expected value, and a report indicating that the assignment statement is a part dependent on a variable memory system is output.
    Type: Grant
    Filed: February 26, 2010
    Date of Patent: September 11, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuji Ishikawa, Yutaka Ota, Yu Nakanishi
  • Patent number: 7946723
    Abstract: Disclosed is a backlight device for illuminating a transmissive color liquid crystal display panel from its backside with white light. The backlight device includes, as a light source, a plural number of principal light emitting diode units 21mn, and a plural number of subsidiary light emitting diode units 21mn, where m and n are natural numbers. Each principal light emitting diode unit is made up by a plural number of light emitting diodes (21) arrayed in a string and emits white light of preset chromaticity. Each subsidiary light emitting diode unit is made up by a plural number of light emitting diodes (21) arrayed in a string and emits white light of chromaticity in the vicinity of the preset chromaticity. The number of the subsidiary light emitting diode units is smaller than that of the principal light emitting diode units.
    Type: Grant
    Filed: October 24, 2005
    Date of Patent: May 24, 2011
    Assignee: Sony Corporation
    Inventors: Takashi Oku, Takeo Arai, Yutaka Ota, Yasuhiro Tagawa
  • Patent number: 7917899
    Abstract: A program development apparatus includes a storage device configured to store an operation definition defining a program description in a source program subjected to be optimized and a complex intrinsic function including an inline clause describing statements after the optimization. An analyzer is configured to perform a syntax analysis of the complex intrinsic function by reading the complex intrinsic function out of the storage device, so as to detect the operation definition and the inline clause. A code generator is configured to generate an object code from the source program by optimizing a program description corresponding to the operation definition in the source program into the statements in the inline clause.
    Type: Grant
    Filed: February 28, 2006
    Date of Patent: March 29, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yutaka Ota, Atsushi Mizuno
  • Publication number: 20110055818
    Abstract: Every time an assignment statement is executed during performing a simulation according to a second variable memory system, it is determined whether a value interpreted to have the same meaning is assigned to the assignment statement in the simulation according to a first variable memory system and in the simulation according to the second variable memory system. When the value interpreted to have the same meaning is not assigned, the value assigned according to the second variable memory system is overwritten by an expected value, and a report indicating that the assignment statement is a part dependent on a variable memory system is output.
    Type: Application
    Filed: February 26, 2010
    Publication date: March 3, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yuji ISHIKAWA, Yutaka Ota, Yu Nakanishi
  • Publication number: 20100308341
    Abstract: A switching resistance RAM that is highly integrated as well as reduced in a read-out time is realized. There is formed an NPN type bipolar transistor BT composed of a collector layer made of an N-well 11, a base layer made of a P+ type Si layer 12A formed in a surface of the N-well 11, and an emitter layer made of an N+ type Si layer 15 formed in a surface of the P+ type Si layer 12A. Also, there are formed a word line WL0 electrically connected to the N+ type Si layer 15 and bit lines BL1-BL4 intersecting with the word line WL0. Also, there are formed a plurality of switching layers 14 formed on a surface of the P+ type Si layer 12A, each being electrically connected to corresponding each of the bit lines and switching between an ON state and an OFF state and an electric potential fixing line 19A to fix the P+ type Si layer 12A at a predetermined electric potential.
    Type: Application
    Filed: September 8, 2008
    Publication date: December 9, 2010
    Applicant: National University Corporation Tokyo University of Agriculture and Technology
    Inventors: Yoshiyuki Suda, Yutaka Ota
  • Publication number: 20100301301
    Abstract: There is offered a switching resistance RAM that is very much reduced in an occupied area and is highly integrated. Memory cells CEL11-CEL14 are formed corresponding to four intersections of word lines WL0 and WL1 and bit lines BL0 and BL1. Each of the memory cells CEL11-CEL14 are composed of a switching layer 13 formed on a surface of an N+ type Si layer 11. The switching layer 13 is electrically connected to the bit line BL0 or BL1 thereabove through an electrode 14. The switching layer 13 is composed of a SiC layer 13A stacked on the surface of the N+ type Si layer 11 and a Si oxide layer 13B stacked on the SiC layer 13A. A top surface of the Si oxide layer 13B, that is the uppermost layer of the switching layer 13, is electrically connected to the corresponding bit line BL0 or BL1.
    Type: Application
    Filed: September 8, 2008
    Publication date: December 2, 2010
    Applicant: National University Corporation Tokyo University of Agriculture and Technology
    Inventors: Yoshiyuki Suda, Yutaka Ota
  • Patent number: 7808585
    Abstract: A color filter (19) used in a transmissive color liquid crystal display panel of a color liquid crystal display (LCD) apparatus. This color filter (19) is constituted by a tristimulus color filter for wavelength-selecting and transmitting red light, green light and blue light. Mixing of blue color and red color is prohibited by not having the transmission wavelength band of the red filter CFR overlaid substantially on the transmission wavelength band of the blue filter CFB.
    Type: Grant
    Filed: July 12, 2005
    Date of Patent: October 5, 2010
    Assignee: Sony Corporation
    Inventors: Shuichi Haga, Koichiro Kakinuma, Takehiro Nakatsue, Tatsuhiko Matsumoto, Yasuhiro Tagawa, Yutaka Ota, Takashi Oku, Takeo Arai
  • Patent number: 7719852
    Abstract: A high-reliability electronic component without reduction in insulation resistance under high-temperature and high-humidity conditions has satisfactory solderability of external electrodes. The electronic component includes a main body and external electrodes disposed on surfaces of the main body, the external electrodes include underlying electrode layers each containing a metal, alloy layers each disposed on the corresponding underlying electrode layer, Ni plating layers each disposed on the corresponding alloy layer, Ni oxide layers each disposed on the corresponding Ni plating layers, and upper plating layers each disposed on the corresponding Ni oxide layer, each Ni oxide layer having a thickness of about 150 nm or less, and each Ni plating layer having an average particle size of Ni particles of about 2 ?m or more. To form the Ni plating layers having reduced grain boundaries, heat treatment is performed at about 500° C. to about 900° C.
    Type: Grant
    Filed: January 3, 2008
    Date of Patent: May 18, 2010
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Shigeyuki Horie, Yutaka Ota, Jun Nishikawa
  • Patent number: 7707386
    Abstract: A design apparatus for designing a processor re-configurable for an application, includes an analysis unit that analyzes the content of a program to be executed by the processor; a hardware extension unit that searches the program for a part of the program allowing hardware extension in accordance with the analysis results by the analysis unit and generates hardware extension information for the searched part; an extended instruction definition unit that searches the program for a part allowing use of an extended instruction in accordance with the analysis results by the analysis unit and generates definition of an extended instruction for the searched part; and a performance estimation unit that estimates whether or not the performance of the processor satisfies a target performance using at least one of the hardware extension information generated by the hardware extension unit and the definition of the extended instruction generated by the extended instruction definition unit.
    Type: Grant
    Filed: December 17, 2007
    Date of Patent: April 27, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuyoshi Kohno, Atsushi Mizuno, Atsushi Masuda, Ryuichiro Ohyama, Yutaka Ota
  • Patent number: 7663714
    Abstract: Disclosed is a backlight device used for a color liquid crystal display (LCD) apparatus. The red light, green light and blue light, generated by a light source, made up by a red light emitting diode (21R), a green light emitting diode (21G) and a blue light emitting diode (21B), respectively, are mixed together to generate white light. The red light has a half-value width hwr such that 15 nm?hwr?30 nm, and the green light has a half-value width hwg such that 25 nm?hwg?50 nm. The blue light has a half-value width hwb such that 15 nm?hwb?30 nm. The white light illuminates a transmissive color liquid crystal display panel (10) from its back side. The transmissive color liquid crystal display panel includes a color filter (19) made up by a tristimulus filter for wavelength-selecting and transmitting red light, green light and blue light.
    Type: Grant
    Filed: August 9, 2005
    Date of Patent: February 16, 2010
    Assignee: Sony Corporation
    Inventors: Shuichi Haga, Koichiro Kakinuma, Takehiro Nakatsue, Tatsuhiko Matsumoto, Yasuhiro Tagawa, Yutaka Ota, Takashi Oku, Takeo Arai
  • Patent number: 7657878
    Abstract: A compiler includes: a syntax analyzer analyzing whether or not an operation described in a source program conforms to grammatical rules, and analyzing whether or not a combination of the operations defines an intrinsic function and details of processing operations of the intrinsic function; an intrinsic function definition database storing a definition of the intrinsic function and the details of the processing operations of the intrinsic function, as analyzed by the syntax analyzer; a code generator generating machine instructions from the source program based on a result of the processing of the syntax analyzer; and a code optimizer optimizing the machine instructions to machine instructions corresponding to the details of the processing operations of the intrinsic function, if a string of the machine instructions generated by the code generator are in agreement with the details of the processing operations of the intrinsic function stored in the intrinsic function definition database.
    Type: Grant
    Filed: March 24, 2004
    Date of Patent: February 2, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yutaka Ota
  • Publication number: 20090138862
    Abstract: A program parallelization supporting apparatus determines a determinacy in at least one dependency relationship of a data dependency, a control dependency and a pointer dependency in a program, extracts a critical path in the program, and extracts a processing instruction which exists on the critical path and has a non-deterministic determinacy in the dependency relationship. Furthermore, if a process related to a path of the extracted non-deterministic processing instruction is parallelized and the path of the non-deterministic processing instruction is deleted, the program parallelization supporting apparatus outputs parallelization labor hour information depending on the number of dependency relationships disturbing the parallelization and parallelization effect information depending on the number of processing instructions which are shortened by the parallelization.
    Type: Application
    Filed: September 16, 2008
    Publication date: May 28, 2009
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Ken Tanabe, Yutaka Ota, Nobu Matsumoto
  • Publication number: 20080285268
    Abstract: Disclosed is a backlight device for illuminating a transmissive color liquid crystal display panel from its backside with white light. The backlight device includes, as a light source, a plural number of principal light emitting diode units 21mn, and a plural number of subsidiary light emitting diode units 21mn, where m and n are natural numbers. Each principal light emitting diode unit is made up by a plural number of light emitting diodes (21) arrayed in a string and emits white light of preset chromaticity. Each subsidiary light emitting diode unit is made up by a plural number of light emitting diodes (21) arrayed in a string and emits white light of chromaticity in the vicinity of the preset chromaticity. The number of the subsidiary light emitting diode units is smaller than that of the principal light emitting diode units.
    Type: Application
    Filed: October 24, 2005
    Publication date: November 20, 2008
    Inventors: Takashi Oku, Takeo Arai, Yutaka Ota, Yasuhiro Tagawa
  • Publication number: 20080186433
    Abstract: A color filter (19) used in a transmissive color liquid crystal display panel of a color liquid crystal display (LCD) apparatus. This color filter (19) is constituted by a tristimulus color filter for wavelength-selecting and transmitting red light, green light and blue light. Mixing of blue color and red color is prohibited by not having the transmission wavelength band of the red filter CFR overlaid substantially on the transmission wavelength band of the blue filter CFB.
    Type: Application
    Filed: July 12, 2005
    Publication date: August 7, 2008
    Inventors: Shuichi Haga, Koichiro Kakinuma, Takehiro Nakatsue, Tatsuhiko Matsumoto, Yasuhiro Tagawa, Yutaka Ota, Takashi Oku, Takeo Arai
  • Publication number: 20080118721
    Abstract: A high-reliability electronic component without reduction in insulation resistance under high-temperature and high-humidity conditions has satisfactory solderability of external electrodes. The electronic component includes a main body and external electrodes disposed on surfaces of the main body, the external electrodes include underlying electrode layers each containing a metal, alloy layers each disposed on the corresponding underlying electrode layer, Ni plating layers each disposed on the corresponding alloy layer, Ni oxide layers each disposed on the corresponding Ni plating layers, and upper plating layers each disposed on the corresponding Ni oxide layer, each Ni oxide layer having a thickness of about 150 nm or less, and each Ni plating layer having an average particle size of Ni particles of about 2 ?m or more. To form the Ni plating layers having reduced grain boundaries, heat treatment is performed at about 500° C. to about 900° C.
    Type: Application
    Filed: January 3, 2008
    Publication date: May 22, 2008
    Applicant: MURATA MANUFACTURING CO., LTD.
    Inventors: Shigeyuki HORIE, Yutaka OTA, Jun NISHIKAWA
  • Publication number: 20080104365
    Abstract: A design apparatus for designing a processor re-configurable for an application, includes an analysis unit that analyzes the content of a program to be executed by the processor; a hardware extension unit that searches the program for a part of the program allowing hardware extension in accordance with the analysis results by the analysis unit and generates hardware extension information for the searched part; an extended instruction definition unit that searches the program for a part allowing use of an extended instruction in accordance with the analysis results by the analysis unit and generates definition of an extended instruction for the searched part; and a performance estimation unit that estimates whether or not the performance of the processor satisfies a target performance using at least one of the hardware extension information generated by the hardware extension unit and the definition of the extended instruction generated by the extended instruction definition unit.
    Type: Application
    Filed: December 17, 2007
    Publication date: May 1, 2008
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kazuhyoshi Kohno, Atsushi Mizuno, Atsushi Masuda, Ryuichiro Ohyama, Yutaka Ota