Abstract: A design apparatus for designing a configurable processor for an application, includes an analysis unit that analyzes the content of a program to be executed by the processor; a hardware extension unit that searches the program for a part of the program allowing hardware extension in accordance with the analysis results by the analysis unit and generates hardware extension information for the searched part; an extension instruction definition unit that searches the program for a part allowing use of an extension instruction in accordance with the analysis results by the analysis unit and generates definition of an extension instruction for the searched part; and a performance estimation unit that estimates whether or not the performance of the processor satisfies a target performance using at least one of the hardware extension information generated by the hardware extension unit and the definition of the extension instruction generated by the extension instruction definition unit.

Abstract: Disclosed is a backlight device used for a color liquid crystal display (LCD) apparatus. The red light, green light and blue light, generated by a light source, made up by a red light emitting diode (21R), a green light emitting diode (21G) and a blue light emitting diode (21B), respectively, are mixed together to generate white light. The red light has a half-value width hwr such that 15 nm?hwr?30 nm, and the green light has a half-value width hwg such that 25 nm?hwg?50 nm. The blue light has a half-value width hwb such that 15 nm?hwb?30 nm. The white light illuminates a transmissive color liquid crystal display panel (10) from its back side. The transmissive color liquid crystal display panel includes a color filter (19) made up by a tristimulus filter for wavelength-selecting and transmitting red light, green light and blue light.

Abstract: A program development apparatus includes a storage device configured to store an operation definition defining a program description in a source program subjected to be optimized and a complex intrinsic function including an inline clause describing statements after the optimization. An analyzer is configured to perform a syntax analysis of the complex intrinsic function by reading the complex intrinsic function out of the storage device, so as to detect the operation definition and the inline clause. A code generator is configured to generate an object code from the source program by optimizing a program description corresponding to the operation definition in the source program into the statements in the inline clause.

Abstract: An instruction generator comprising a storage device configured to store a machine instruction function incorporating both an operation definition defining a program description in a source program targeted for substitution to a SIMD instruction, and the SIMD instruction. A parallelism analyzer is configured to analyze the source program so as to detect operators applicable to parallel execution, and to generate parallelism information indicating the set of operators applicable to parallel execution. A SIMD instruction generator is configured to perform a matching determination between an instruction generating rule for the SIMD instruction and the parallelism information, and to read the machine instruction function out of the storage device in accordance with a result of the matching determination.

Abstract: A design apparatus for designing a configurable processor for an application, includes an analysis unit that analyzes the content of a program to be executed by the processor; a hardware extension unit that searches the program for a part of the program allowing hardware extension in accordance with the analysis results by the analysis unit and generates hardware extension information for the searched part; an extension instruction definition unit that searches the program for a part allowing use of an extension instruction in accordance with the analysis results by the analysis unit and generates definition of an extension instruction for the searched part; and a performance estimation unit that estimates whether or not the performance of the processor satisfies a target performance using at least one of the hardware extension information generated by the hardware extension unit and the definition of the extension instruction generated by the extension instruction definition unit.

Abstract: A compiler includes: a syntax analyzer analyzing whether or not an operation described in a source program conforms to grammatical rules, and analyzing whether or not a combination of the operations defines an intrinsic function and details of processing operations of the intrinsic function; an intrinsic function definition database storing a definition of the intrinsic function and the details of the processing operations of the intrinsic function, as analyzed by the syntax analyzer; a code generator generating machine instructions from the source program based on a result of the processing of the syntax analyzer; and a code optimizer optimizing the machine instructions to machine instructions corresponding to the details of the processing operations of the intrinsic function, if a string of the machine instructions generated by the code generator are in agreement with the details of the processing operations of the intrinsic function stored in the intrinsic function definition database.

Abstract: A digital recording and reproducing apparatus comprising a cassette number registering circuit (1) for applying different CIDs for respective cassettes, a corresponding control circuit (7) for searching, adding and deleting program data, a cassette number inserting circuit (2) for inserting a CID in the form of a digital signal into the VBI of an analog video signal, a cassette number extracting circuit (3) for extracting a CID from a VBI, magnetic recording and reproducing means (4) for recording and reproducing the analog signal by using a magnetic tape (50), a display number registering circuit (5) for applying an AID which corresponds to a CID and is recognized by a user, a memory circuit (6) for storing program data including a CID, an AID, a starting tape position, an ending tape position and recording start date, a program integrating circuit (76) which makes one AID corresponds to a plurality of CIDs, and, keeps programs having later date and deletes programs having older date when the recorded magnet

Abstract: By perfectly preventing a particle from being attached on a silicon wafer or a silicon epitaxial wafer before and after the silicon epitaxial growth, pit formation on the silicon epitaxial layer in RCA cleaning is prevented from occurring. A pretreatment chamber, a vapor phase growth chamber and an aftertreatment chamber are mutually connected by a transport path whose interior is clean while being isolated from the outside environment. In the pretreatment chamber, megasonic cleaning using O3 added water is conducted (step S2); in the vapor growth chamber, removal of a chemical silicon oxide film C by pre-bake (step S4) and formation of a high quality silicon epitaxial layer E are conducted (step S5); and in the aftertreatment chamber, passivation of the silicon epitaxial layer E is conducted by O3 water cleaning or SC1 cleaning (step S7).

Abstract: An apparatus for manufacturing a semiconductor material includes a load-lock chamber which can contain a cassette for holding at least one wafer for taking the wafer into or out of the apparatus, a process furnace for conducting a treatment to the wafer, and a transfer chamber for transferring the wafer between the load-lock chamber and the process furnace, wherein the apparatus further includes a pressure detector for detecting a pressure difference between in the process furnace and in the transfer chamber, and a gas flow controller for controlling a flow rate of a gas flow supplied to the transfer chamber in accordance with results of detection by the pressure detector.

Abstract: A vapor-phase growth plant which has a dopant gas supplying apparatus comprising a plurality of dopant gas supplying containers, and a multiple stage gas flow subsystem with a plurality of dopant gas supply conduits therein, of which said dopant gas supply conduits form a tournament-style network with a plurality of confluences on which the dopant gas supply conduits are united and the gas flows therein are merged for subjection to even mixing which results in gradual decreasing of the number of the dopant gas supply conduits as the dopant gas flows proceed in the multiple stage gas flow subsystem. Together with the equipped pressure reducing valves, the dopant gas which is highly evened in its pressure and its concentration can be supplied to the vapor-phase growth apparatus, thereby affording stable production of vapor-phase growth products with extremely lessened quality variance.

Abstract: An electron gun for a color CRT has three cathodes disposed in parallel to each other, first to fifth grid electrodes and a convergence deflector. The electron gun is additionally provided with a tetrode magnetic field generator including a pair of permanent magnets having an astigmatic effect of the central beam of the electron gun on the cathode side of the convergence deflector. An astigmatism eliminator is provided to cancel astigmatic aberration of the side beams of the electron gun near the position where the electron beams are converged. The astigmatism eliminator is composed of a fifth grid electrode whose entrance has an electron beam passing hole of nearly elliptic shape.

Abstract: A synchronizer ring has a frictional material and oil grooves extending on the frictional surface of the frictional material in a longitudinal direction and a circumferential direction, and in the oil grooves, the fiber layer of the frictional material is substantially continuous. The oil grooves are formed simultaneously by a shaping apparatus including an arrangement of longitudinal and circumferential groove punches which are simultaneously forced outwardly from a punch holder by a cooperative slide member which reciprocates within the punch holder.