Patents by Inventor Yutaka Saitoh

Yutaka Saitoh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20030214669
    Abstract: A method of differentiating each of a set of prints of a document is presented. A start command that instructs start of printing of one set of prints is sent to a printer. The printer prints the one set of the prints on, for example, a paper. Once the printing of the one set of the prints is over, an end command that instructs end of the printing is sent to the printer. Printing of a next set of prints can be started after this.
    Type: Application
    Filed: March 21, 2003
    Publication date: November 20, 2003
    Inventor: Yutaka Saitoh
  • Publication number: 20030181722
    Abstract: Compounds having immunosuppressive activity, cell growth inhibitory activity, anti-tumor activity, etc.
    Type: Application
    Filed: November 7, 2002
    Publication date: September 25, 2003
    Applicant: Kyowa Hakko Kogyo Co., Ltd.
    Inventors: Tsutomu Akama, Hiroyuki Nagata, Atsuhiro Hasegawa, Harumi Ue, Isami Takahashi, Yutaka Saitoh, Kenichi Mochida, Shun-Ichi Ikeda, Yutaka Kanda
  • Patent number: 6613774
    Abstract: LK6-A derivatives which have immmunosuppressive activity, cell growth inhibitory activity, anti-tumor activity, etc. and which are represented by general formula (I): as defined herein, and pharmaceutically acceptable salts thereof.
    Type: Grant
    Filed: January 2, 2001
    Date of Patent: September 2, 2003
    Assignee: Kyowa Hakko Kogyo Co., Ltd.
    Inventors: Tsutomu Akama, Hiroyuki Nagata, Atsuhiro Hasegawa, Harumi Ue, Isami Takahashi, Yutaka Saitoh, Kenichi Mochida, Shun-ichi Ikeda, Yutaka Kanda
  • Patent number: 6498376
    Abstract: A MISFET is provided with a segmented channel comprising regions in which the channel is inverted by a first gate voltage and regions in which the channel is inverted by a second gate voltage. The MISFET is formed in a semiconductor substrate having a first conductivity type and the first inversion region of the channel has a first impurity concentration determined by the surface concentration of the substrate. The second inversion region of the channel has a second impurity concentration determined by doping an impurity to the region selected by a photolithographic process. The first and second inversion regions may be divided into a plurality of plane shapes and the threshold voltage of the MISFET is set to a desired value in accordance with the plane area ratio of the first and second inversion regions.
    Type: Grant
    Filed: June 2, 1995
    Date of Patent: December 24, 2002
    Assignee: Seiko Instruments INC
    Inventors: Masanori Miyagi, Haruo Konishi, Kazuaki Kubo, Yoshikazu Kojima, Toru Shimizu, Yutaka Saitoh, Toru Machida, Tetsuya Kaneko
  • Publication number: 20020190689
    Abstract: To provide a power supply apparatus that replaces a dry battery by detecting electric field energy in a free space, rectifying the energy, extracting the energy as electric power, and accumulating the electric power. In particular, there is provided a power supply apparatus that is useful for a portable electronic equipment. An electromagnetic energy conversion unit collects a radio wave propagating in the air and converts collected electromagnetic energy into electric power. A rectifying unit generates electric power having a DC waveform by rectifying electric power having an AC waveform and charges the rectified electric power having the DC waveform into a secondary battery. An electric load is supplied with the rectified electric power having the DC waveform or with electric power having a DC waveform discharged from the secondary battery.
    Type: Application
    Filed: May 16, 2002
    Publication date: December 19, 2002
    Inventors: Chiaki Nakamura, Kazuo Kato, Yutaka Saitoh, Kazuo Matsubara, Tsutomu Tanaka
  • Patent number: 6320474
    Abstract: A MOS-type capacitor includes a semiconductor substrate of a first conductive type serving as a first electrode, a conductor layer formed on the semiconductor substrate via a capacitive insulation film and serving as a second electrode, and an impurity region of a second conductive type formed in the vicinity of the surface of the semiconductor substrate at a location in proximity to a region facing the conductor layer. The MOS-type capacitor is used as a variable capacitor in a VCO (voltage-controlled oscillator) having a widened frequency range.
    Type: Grant
    Filed: December 28, 1999
    Date of Patent: November 20, 2001
    Assignee: Interchip Corporation
    Inventors: Masaaki Kamiya, Yutaka Saitoh
  • Patent number: 6306709
    Abstract: In a MISFET, areas where a channel surface of a channel region is inverted by a first gate voltage and areas where the channel surface is inverted by a second gate voltage are provided in the channel region of the MISFET in plane as components thereof. The channel region 104 having a first impurity concentration determined by a surface concentration of a P-type semiconductor substrate and a channel region 105 having a second impurity concentration determined by doping an impurity to the region selected by a pattern 106 of a mask for doping impurity by ion implantation and others are provided in a channel region of an N-type MOSFET on the P-type semiconductor substrate. The channel region 104 having the first impurity concentration and the channel region 105 having the second impurity concentration are divided into a plurality of plane shapes.
    Type: Grant
    Filed: March 16, 1999
    Date of Patent: October 23, 2001
    Assignee: Seiko Instruments Inc.
    Inventors: Masanori Miyagi, Haruo Konishi, Kazuaki Kubo, Yoshikazu Kojima, Toru Shimizu, Yutaka Saitoh, Toru Machida, Tetsuya Kaneko
  • Patent number: 6255700
    Abstract: A semiconductor device comprises a depletion-type NMOS transistor having a source region, a drain region connected to a power supply line, and a gate electrode connected to a ground line. An enhancement-type NMOS transistor has a source connected to the ground line, a drain connected in series with the source of the depletion-type MOS transistor between the power supply line and the ground line to define an output terminal, and a gate electrode connected directly to the output terminal.
    Type: Grant
    Filed: January 14, 1997
    Date of Patent: July 3, 2001
    Assignee: Seiko Instruments Inc.
    Inventors: Yoshifumi Yoshida, Shinichi Yoshida, Yutaka Saitoh, Jun Osanai
  • Patent number: 6191005
    Abstract: A process for producing a semiconductor device comprises heat-treating an oxygen-containing silicon substrate in an inert atmosphere to change a concentration of oxygen contained in the silicon substrate to within a range of 5×1017/cm3 to 10×1017/cm3, and heat treating the silicon substrate in an oxidative atmosphere to form a silicon oxide film.
    Type: Grant
    Filed: September 6, 1995
    Date of Patent: February 20, 2001
    Assignee: Seiko Instruments Inc.
    Inventors: Yutaka Saitoh, Jun Osanai
  • Patent number: 6158283
    Abstract: A semiconductor acceleration sensor comprises a cantilever structure formed from a semiconductor wafer and having a first surface for receiving an acceleration force, a second surface disposed generally orthogonal to the first surface, and strain sensing portions disposed on the second surface. A supporting body supports the cantilever structure. A plurality of bridge circuits are disposed on the second surface of the rectangular parallelepiped shaped structure. Each of the bridge circuits has a plurality of the strain sensing portions.
    Type: Grant
    Filed: February 7, 1997
    Date of Patent: December 12, 2000
    Assignee: Seiko Instruments R&D Center Inc.
    Inventors: Masataka Shinogi, Yutaka Saitoh, Kenji Kato
  • Patent number: 6124148
    Abstract: A method of manufacturing a semiconductor acceleration sensor comprises forming a strain sensing section on a surface of a semiconductor wafer, fixing the semiconductor wafer to a cooled fixing stage, cutting out a structural body having the strain sensing section from the semiconductor wafer, and connecting a support member to the structural body cut from the semiconductor wafer.
    Type: Grant
    Filed: April 18, 1997
    Date of Patent: September 26, 2000
    Assignee: Seiko Instruments R&D Center Inc.
    Inventors: Masataka Shinogi, Yutaka Saitoh, Kenji Kato
  • Patent number: 6114685
    Abstract: A solid-state radiation detecting device comprises an insulation layer having a pair of opposed surfaces. First and second single crystal silicon semiconductors are disposed on respective ones of the opposed surfaces of the insulating layer. A photoelectric conversion element is disposed on the first single crystal silicon semiconductor. A signal processing circuit having a charge transfer device is disposed on the second single crystal silicon semiconductor.
    Type: Grant
    Filed: January 22, 1998
    Date of Patent: September 5, 2000
    Assignee: Seiko Instruments R&D Center Inc.
    Inventors: Keiji Sato, Yutaka Saitoh
  • Patent number: 6110634
    Abstract: The present invention relates to an electrophotographic toner containing a binder resin having an acid value in the range of from 0.1 to 50 and a novel compound of zirconium complex or salt useful as a charge control agent for the electrophotographic toner.
    Type: Grant
    Filed: July 30, 1999
    Date of Patent: August 29, 2000
    Assignee: Hodogaya Chemical Co., Ltd.
    Inventors: Masataka Sawano, Taito Muraoka, Yutaka Saitoh, Hiroyoshi Yamaga, Rie Murakami
  • Patent number: 6097064
    Abstract: An improvement of a resistance to electrostatic discharge of a semiconductor integrated circuit device is aimed. An IC having a high ESD immunity is realized by causing a surface concentration of N type impurities in a drain area of an N-channel type MOS transistor to be more than 5 E 18/cm.sup.3 in maximum in the direction of gate electrode of a gate electrode terminal and to have a monotonous concentration profile in which there is no kink in a portion less than 5 E 18/cm.sup.3 in the surface direction.
    Type: Grant
    Filed: June 12, 1997
    Date of Patent: August 1, 2000
    Assignee: Seiko Instruments Inc.
    Inventors: Yutaka Saitoh, Jun Osanai
  • Patent number: 6057585
    Abstract: A semiconductor acceleration sensor comprises a base having a first surface for receiving an acceleration force and a second surface disposed generally perpendicular to the first surface. A first detector is disposed on the second surface of the base for detecting an acceleration force in a horizontal direction of the base. A second detector is disposed on the second surface of the base for detecting an acceleration force in a vertical direction of the base. A support member is connected to one end of the base for supporting and fixing the base.
    Type: Grant
    Filed: March 12, 1998
    Date of Patent: May 2, 2000
    Assignee: Seiko Instruments R&D Center Inc.
    Inventors: Masataka Shinogi, Yutaka Saitoh, Kenji Kato
  • Patent number: 6046461
    Abstract: An IC is configured by using a circuit form comprising a CMOS and also a new current inverter element, thereby to reduce current consumption of ICs having a function of converting an output from a photodiode or the like to a voltage and a function of amplifying the output.
    Type: Grant
    Filed: May 30, 1997
    Date of Patent: April 4, 2000
    Assignee: Seiko Instruments R&D Center Inc.
    Inventors: Yutaka Saitoh, Yuji Yamamoto, Hirokazu Ikeda
  • Patent number: 6013940
    Abstract: A resistor ladder network may be formed with a reduced space on a semiconductor substrate by patterning a plurality of layers of resistive polycrystalline silicon films spaced by insulating layers. Such a device includes a first insulating film formed on a semiconductor substrate, one or more serial-connected first resistors formed in a first polycrystalline silicon film provided on the semiconductor substrate via the first insulating film, a second insulating film provided on the first polycrystalline silicon film, one or more series-connected second resistors formed in a second polycrystalline silicon film provided apart from the first polycrystalline silicon film via the second insulating film, the second polycrystalline silicon film being connected to the first polycrystalline silicon film. A third insulating film is provided over the second polycrystalline silicon film, and metal wires provided on a surface of the second polycrystalline silicon film via contact holes formed in the third insulating film.
    Type: Grant
    Filed: August 18, 1995
    Date of Patent: January 11, 2000
    Assignee: Seiko Instruments Inc.
    Inventors: Hirofumi Harada, Jun Osanai, Yoshikazu Kojima, Yutaka Saitoh
  • Patent number: 6006606
    Abstract: A semiconductor acceleration sensor comprises a sensor element having a first surface for receiving an acceleration force and second opposite surfaces disposed generally perpendicular to the first surface, a support for supporting and fixing the sensor element, and a detecting device disposed on the second opposite surfaces of the sensor element for detecting a variation of a physical quantity due to an acceleration force applied to the first surface of the sensor element.
    Type: Grant
    Filed: April 18, 1997
    Date of Patent: December 28, 1999
    Assignee: Seiko Instruments R&D Center Inc.
    Inventors: Masataka Shinogi, Yutaka Saitoh, Kenji Kato
  • Patent number: 6005275
    Abstract: A semiconductor device comprises a semiconductor acceleration sensor having a cantilever made of a semiconductor material, a supporter for supporting the cantilever, and diffused resistors disposed on the cantilever. An acceleration detecting device detects a displacement of the cantilever based on acceleration forces applied to the cantilever and on changes of resistance values of the diffused resistors.
    Type: Grant
    Filed: August 23, 1995
    Date of Patent: December 21, 1999
    Assignee: Seiko Instruments Inc.
    Inventors: Masataka Shinogi, Yutaka Saitoh, Yoshifumi Yoshida, Hirofumi Harada, Kenji Katoh
  • Patent number: 6001667
    Abstract: A method of manufacturing a semiconductor detector for detecting light and radiation comprises the steps of providing a first semiconductor substrate of a first conductivity type, attaching a second substrate to the first semiconductor substrate through an insulating film, grinding the first semiconductor substrate from a surface thereof to a predetermined thickness, forming a MOS transistor on the ground surface of the first semiconductor substrate, removing the second substrate, and forming electrodes on the first semiconductor substrate for forming a depletion layer.
    Type: Grant
    Filed: June 3, 1996
    Date of Patent: December 14, 1999
    Assignee: Seiko Instruments Inc.
    Inventors: Yutaka Saitoh, Masahiro Inoue, Junko Yamanaka, Hirokazu Ikeda