Patents by Inventor Yutaka Takafuji

Yutaka Takafuji has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110272694
    Abstract: The present invention is intended to provide a glass substrate (20), made of an insulating material, which can constitute a semiconductor apparatus (10) by transferring a single crystal silicon film (50) or a substrate including a semiconductor device onto a surface (24) of the insulating substrate, a transferred surface (26) being part of the surface (24), the single crystal silicon film (50) capable of being provided on the transferred surface (26), and the transferred surface (26) having an arithmetic mean roughness of not more than 0.4 nm.
    Type: Application
    Filed: September 8, 2008
    Publication date: November 10, 2011
    Inventors: Michiko Takei, Shin Matsumoto, Kazuhide Tomiyasu, Yasumori Fukushima, Yutaka Takafuji
  • Publication number: 20110269284
    Abstract: The present invention provides a semiconductor substrate, which comprises a singlecrystalline Si substrate which includes an active layer having a channel region, a source region, and a drain region, the singlecrystalline Si substrate including at least a part of a device structure not containing a well-structure or a channel stop region; a gate insulating film formed on the singlecrystalline Si substrate; a gate electrode formed on the gate insulating film; a LOCOS oxide film whose thickness is more than a thickness of the gate insulating film, the LOCOS oxide film being formed on the singlecrystalline Si substrate by surrounding the active layer; and an insulating film formed over the gate electrode and the LOCOS oxide film.
    Type: Application
    Filed: June 1, 2011
    Publication date: November 3, 2011
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Yutaka Takafuji, Yasumori Fukushima, Masao Moriguchi
  • Publication number: 20110241006
    Abstract: Provided is a liquid crystal display device (1) comprising a substrate (2), a base coating film (3) disposed on the substrate (2), a base insulating film (4) disposed on the base coating film (3), and a semiconductor film (20) disposed on the base insulating film (4) and made of a polysilicon film. Below the semiconductor film (20), a light-shielding film (28) is formed, which is embedded in the base coating film (3).
    Type: Application
    Filed: August 25, 2009
    Publication date: October 6, 2011
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Masahiro Mitani, Yutaka Takafuji
  • Publication number: 20110241174
    Abstract: Provided is a semiconductor device manufacturing method wherein the following steps are performed; a step of forming at least a part of an element on a base body layer, a step of forming a peeling layer, a step of forming a planarizing film; a step of forming a die by separating the base body layer at a separating region; a step of bonding the die to a substrate by bonding the die on the planarizing film; and a step of peeling and removing a part of the base body layer along the peeling layer. Prior to the step of forming the die, a step of forming a groove opened on the surface of the planarizing film such that at least a part of the separating region is included on the bottom surface of the groove, and forming the die such that the die has a polygonal outer shape wherein all the internal angles are obtuse by forming the groove is performed.
    Type: Application
    Filed: August 21, 2009
    Publication date: October 6, 2011
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Michiko Takei, Yasumori Fukushima, Kazuhide Tomiyasu, Shin Matsumoto, Kazuo Nakagawa, Yutaka Takafuji
  • Patent number: 8017492
    Abstract: A method for fabricating a semiconductor device according to the present invention is a method for fabricating a semiconductor device including a substrate layer including a plurality of first regions each having an active region and a plurality of second regions each being provided between adjacent ones of the first region. The fabrication method includes an isolation insulation film formation step of forming an isolation insulation film in each of the second regions so that a surface of the isolation insulation film becomes at the same height as that of a surface of a gate oxide film covering the active region, a peeling layer formation step of forming a peeling layer by ion-implanting hydrogen into the substrate layer after the isolation insulation film formation step, and a separation step of separating part of the substrate layer along the peeling layer.
    Type: Grant
    Filed: August 12, 2008
    Date of Patent: September 13, 2011
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yasumori Fukushima, Masao Moriguchi, Yutaka Takafuji
  • Patent number: 8008205
    Abstract: A method of the present invention includes a first planarization film formation step of forming, in at least part of a flat portion of the second regions, a first planarization film so as to have a uniform thickness; a second planarization film formation step of forming a second planarization film between the first planarization films to be coplanar with a surface of the first planarization film; a peeling layer formation step of forming a peeling layer by ion implantation of a peeling material into the base layer via the first planarization film or the second planarization film; and a separation step of separating part of the base layer along the peeling layer.
    Type: Grant
    Filed: October 13, 2006
    Date of Patent: August 30, 2011
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yasumori Fukushima, Yutaka Takafuji, Michiko Takei, Kazuhide Tomiyasu
  • Patent number: 7989304
    Abstract: A transistor formed on a monocrystalline Si wafer is temporarily transferred onto a first temporary supporting substrate. The first temporarily supporting substrate is heat-treated at high heat so as to repair crystal defects generated in a transistor channel of the monocrystalline Si wafer when transferring the transistor. The transistor is then made into a chip and transferred onto a TFT substrate. In order to transfer the transistor which has been once separated from the monocrystalline Si wafer, a different method from a stripping method utilizing ion doping is employed.
    Type: Grant
    Filed: December 13, 2006
    Date of Patent: August 2, 2011
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Michiko Takei, Kazuhide Tomiyasu, Yasumori Fukushima, Yutaka Takafuji
  • Publication number: 20110163297
    Abstract: A fabrication method is provided for a core-shell-shell (CSS) nanowire transistor (NWT). The method provides a cylindrical CSS nanostructure with a semiconductor core, an insulator shell, and a conductive shell. The CSS nanostructure has a lower hemicylinder overlying a substrate surface. A first insulating film is conformally deposited overlying the CSS nanostructure and anisotropically plasma etched. Insulating reentrant stringers are formed adjacent the nanostructure lower hemicylinder. A conductive film is conformally deposited and selected regions are anisotropically plasma etched, forming conductive film gate straps overlying a gate electrode in a center section of the CSS nanostructure. An isotropically etching removes the insulating reentrant stringers adjacent the center section of the CSS nanostructure, and an isotropically etching of the conductive shell overlying the S/D regions is performed. A screen oxide layer is deposited over the CSS nanostructure.
    Type: Application
    Filed: March 17, 2011
    Publication date: July 7, 2011
    Inventors: Mark A. Crowder, Yutaka Takafuji
  • Patent number: 7935599
    Abstract: A method is provided for removing reentrant stringers in the fabrication of a nanowire transistor (NWT). The method provides a cylindrical nanostructure with an outside surface axis overlying a substrate surface. The nanostructure includes an insulated semiconductor core. A conductive film is conformally deposited overlying the nanostructure, to function as a gate strap or a combination gate and gate strap. A hard mask insulator is deposited overlying the conductive film and selected regions of the hard mask are anisotropically plasma etched. As a result, a conductive film gate electrode is formed substantially surrounding a cylindrical section of nanostructure. Inadvertently, conductive film reentrant stringers may be formed adjacent the nanostructure outside surface axis, made from the conductive film. The method etches, and so removes the conductive film reentrant stringers.
    Type: Grant
    Filed: April 4, 2007
    Date of Patent: May 3, 2011
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Mark A. Crowder, Yutaka Takafuji
  • Patent number: 7923310
    Abstract: A fabrication method is provided for a core-shell-shell (CSS) nanowire transistor (NWT). The method provides a cylindrical CSS nanostructure with a semiconductor core, an insulator shell, and a conductive shell. The CSS nanostructure has a lower hemicylinder overlying a substrate surface. A first insulating film is conformally deposited overlying the CSS nanostructure and anisotropically plasma etched. Insulating reentrant stringers are formed adjacent the nanostructure lower hemicylinder. A conductive film is conformally deposited and selected regions are anisotropically plasma etched, forming conductive film gate straps overlying a gate electrode in a center section of the CSS nanostructure. An isotropically etching removes the insulating reentrant stringers adjacent the center section of the CSS nanostructure, and an isotropically etching of the conductive shell overlying the S/D regions is performed. A screen oxide layer is deposited over the CSS nanostructure.
    Type: Grant
    Filed: July 17, 2007
    Date of Patent: April 12, 2011
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Mark A. Crowder, Yutaka Takafuji
  • Patent number: 7919392
    Abstract: On an SOI substrate, a hydrogen ion implantation section in which distribution of hydrogen ions peaks in a BOX layer (buried oxide film layer), and a single-crystal silicon thin-film transistor are formed. Then this SOI substrate is bonded with an insulating substrate. Subsequently, the SOI substrate is cleaved at the hydrogen ion implantation section by carrying out heat treatment, so that an unnecessary part of the SOI substrate is removed, Furthermore, the BOX layer remaining on the single-crystal silicon thin-film transistor is removed by etching. With this, it is possible to from a single-crystal silicon thin-film device on an insulating substrate, without using an adhesive. Moreover, it is possible to provide a semiconductor device which has no surface damage and includes a single-crystal silicon thin film which is thin and uniform in thickness.
    Type: Grant
    Filed: July 9, 2009
    Date of Patent: April 5, 2011
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yutaka Takafuji, Takashi Itoga
  • Publication number: 20110058126
    Abstract: With reference to a direction perpendicular to a direction of forming electrodes to which a voltage can be applied, fine structures are each arranged within ±5 degrees at a substantially even interval, and a semiconductor element is formed by using the fine structures. On an insulating substrate, at least two electrodes are arranged at a predetermined interval, and there are formed one or more fine structure arranging regions, each of which is formed by a unit of the two electrodes. A semiconductor element electrode is made in contact with the plurality of the fine structures, each having two ends in contact with the two electrodes and a length in a longitudinal direction of a nano order to a micron order, and arranged within ±5 degrees with reference to the direction perpendicular to the direction of forming the electrodes.
    Type: Application
    Filed: February 10, 2009
    Publication date: March 10, 2011
    Inventors: Yasunobu Okada, Akihide Shibata, Yoshiharu Nakajima, Hiroshi Iwata, Ai Naitou, Yutaka Takafuji, Tetsu Negishi
  • Patent number: 7897443
    Abstract: The present invention provides a production method of a semiconductor device, which can improve characteristics of a semiconductor element including a single crystal semiconductor layer formed by transferring on an insulating substrate. The present invention is a production method of a semiconductor device comprising a single crystal semiconductor layer formed on an insulating substrate, the production method comprising the steps of: implanting a substance for separation into a single crystal semiconductor substrate, thereby forming a separation layer; transferring a part of the single crystal semiconductor substrate, separated at the separation layer, onto the insulating substrate, thereby forming the single crystal semiconductor layer; forming a hydrogen-containing layer on at least one side of the single crystal semiconductor layer; and diffusing hydrogen from the hydrogen-containing layer to the single crystal semiconductor layer.
    Type: Grant
    Filed: January 17, 2006
    Date of Patent: March 1, 2011
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Masao Moriguchi, Yutaka Takafuji, Steven Roy Droes
  • Publication number: 20110042693
    Abstract: A semiconductor device (10) includes a support substrate (14), an adhered device part (11) adhered to the support substrate (14), a multilayer device part (13) stacked on the adhered device part (11), and an adjacent device part (12) formed in a region adjacent to the adhered device part on the support substrate (14). The adhered device part (11), the multilayer device part (13), and the adjacent device part (12) are electrically connected to one another.
    Type: Application
    Filed: April 9, 2009
    Publication date: February 24, 2011
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Kenshi Tada, Yutaka Takafuji, Yasumori Fukushima, Kazuhide Tomiyasu, Michiko Takei, Kazuo Nakagawa, Shin Matsumoto
  • Patent number: 7884367
    Abstract: A polycrystalline Si thin film and a single crystal Si thin film are formed on an SiO2 film deposited on an insulating substrate. A polycrystalline Si layer is grown by thermally crystallizing an amorphous Si thin film so as to form the polycrystalline Si thin film. A single crystal Si substrate, having (a) an SiO2 film thereon and (b) a hydrogen ion implantation portion therein, is bonded to an area of the polycrystalline Si thin film that has been subjected to etching removal, and is subjected to a heating process. Then, the single crystal Si substrate is divided at the hydrogen ion implantation portion in an exfoliating manner, so as to form the single crystal Si thin film. As a result, it is possible to provide a large-size semiconductor device, having the single crystal Si thin film, whose property is stable, at a low cost.
    Type: Grant
    Filed: October 6, 2009
    Date of Patent: February 8, 2011
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yutaka Takafuji, Takashi Itoga
  • Publication number: 20110006376
    Abstract: The present invention provides a semiconductor device capable of improving subthreshold characteristics of a PMOS transistor that is included in a thinned base layer and bonded to another substrate, a production method of such a semiconductor device, and a display device. The semiconductor device of the present invention is a semiconductor device, including: a substrate; and a device part bonded to the substrate, the device part including a base layer and a PMOS transistor, the PMOS transistor including a first electrical conduction path and a first gate electrode, the first electrical conduction path being provided inside the base layer on a side where the first gate electrode is disposed.
    Type: Application
    Filed: March 3, 2009
    Publication date: January 13, 2011
    Inventors: Yasumori Fukushima, Yutaka Takafuji, Masao Moriguchi, Kenshi Tada, Steven Roy Droes
  • Publication number: 20100295105
    Abstract: A method for manufacturing a semiconductor device includes: an element portion formation step of forming an element portion on a base layer; a delaminating layer formation step of forming a delaminating layer in the base layer; a bonding step of bonding the base layer having the element portion to a substrate; and a separation step of separating and removing a portion of the base layer in the depth direction along the delaminating layer by heating the base layer bonded to the substrate. The method further includes, after the separation step, an ion implantation step of ion-implanting a p-type impurity element in the base layer for adjusting the impurity concentration of a p-type region of the element.
    Type: Application
    Filed: September 25, 2008
    Publication date: November 25, 2010
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Yasumori Fukushima, Kazuhide Tomiyasu, Yutaka Takafuji, Kenshi Tada, Michiko Takei
  • Patent number: 7838936
    Abstract: An active matrix substrate includes a glass substrate, a driver portion formed on the glass substrate in a protruding state, a stepped portion formed along a surface of the driver portion and a surface of the glass substrate, an insulating reentrant-angle compensating film formed on a surface of the stepped portion, for compensating for at least a part of a reentrant-angle shape of the stepped portion, and a wiring layer formed along a surface of the reentrant-angle compensating film and connected to the driver portion.
    Type: Grant
    Filed: March 9, 2006
    Date of Patent: November 23, 2010
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Kazuhide Tomiyasu, Yutaka Takafuji, Masao Moriguchi
  • Publication number: 20100289037
    Abstract: The present invention provides a semiconductor device having a plurality of MOS transistors with controllable threshold values in the same face and easy to manufacture, a manufacturing method thereof and a display device. The invention is a semiconductor device having a plurality of MOS transistors in the same face each having a structure formed by stacking a semiconductor active layer, a gate insulator, and a gate electrode, wherein the semiconductor device includes: an insulating layer stacked on a side opposite to a gate electrode side of the semiconductor active layer; and a conductive electrode stacked on a side opposite to a semiconductor active layer side of the insulating layer and extending over at least two of the plurality of MOS transistors.
    Type: Application
    Filed: October 10, 2008
    Publication date: November 18, 2010
    Inventors: Shin Matsumoto, Yutaka Takafuji, Yasumori Fukushima, kenshi Tada
  • Publication number: 20100283104
    Abstract: An element portion forming step includes an insulating film forming step of forming an insulating film on a surface of a base layer, a conductive layer forming step of uniformly forming a conductive layer on a surface of the insulating film, and an electrode forming step of patterning the conductive layer to form an electrode. A delamination layer forming step of ion implanting a delamination material into the base layer to form a delamination layer is performed before the electrode forming step.
    Type: Application
    Filed: November 25, 2008
    Publication date: November 11, 2010
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Kenshi Tada, Yutaka Takafuji, Yasumori Fukushima, Kazuhide Tomiyasu, Michiko Takei, Kazuo Nakagawa, Shin Matsumoto