Patents by Inventor Yutaka Uemura
Yutaka Uemura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11967358Abstract: Apparatuses, systems, and methods for bias temperature instability (BTI) mitigation. A BTI oscillator provides a periodic BTI signal. A BTI logic circuit generates a BTI pulse signal based on the periodic BTI signal and synchronized to a clock signal. A clock gating circuit passes the clock signal to a clock path when the periodic BTI signal is active. When the memory is in an unclocked mode, where an external clock is not received, the periodic BTI signal is provided to a clock input buffer and passed as the clock signal.Type: GrantFiled: May 26, 2022Date of Patent: April 23, 2024Assignee: Micron Technology, Inc.Inventors: Yoshiya Komatsu, Yutaka Uemura
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Publication number: 20240013823Abstract: Apparatuses for timing control in a write path are disclosed. An example apparatus includes: a clock input circuit that receives a clock signal and provides an internal clock signal; a command decoder that receives command signals and the internal clock signal, and provides an active write command signal when the command signals indicates a write operation; a write latency shifter that receives the write command signal, a latency value and a WICA value, adjusts timing of the write command signal responsive to the latency value and the WICA value, and provides a shifted write command signal; and a write DLL including a delay line that receives the shifted write command signal and provides a delayed write command signal. The write DLL provides the WICA value to set a propagation time from the clock input circuit to the write DLL to be a multiple of a period of the clock signal.Type: ApplicationFiled: July 7, 2022Publication date: January 11, 2024Applicant: Micron Technology, Inc.Inventors: SHINGO MITSUBORI, RYO FUJIMAKI, YUTAKA UEMURA
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Publication number: 20230386529Abstract: In some examples, command decoders may have multiple command paths. In some examples, command signals from one command path may be provided to another command path from a node located between two latches of the command decoder, such as two latches of a flip-flop. In some examples, the command decoder may include separate flip-flops for different command modes. In some examples, the separate flip-flops may be tristate flip-flops. In some examples, the command decoder may include alternate logic circuits rather than a multiplexer.Type: ApplicationFiled: May 24, 2022Publication date: November 30, 2023Applicant: MICRON TECHNOLOGY, INC.Inventors: YUTAKA UEMURA, YOSHIYA KOMATSU
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Publication number: 20230386530Abstract: In some examples, command decoders may have multiple command paths. In some examples, command signals from one command path may be provided to another command path from a node located between two latches of the command decoder, such as two latches of a flip-flop. In some examples, the command decoder may include separate flip-flops for different command modes. In some examples, the separate flip-flops may be tristate flip-flops. In some examples, the command decoder may include alternate logic circuits rather than a multiplexer.Type: ApplicationFiled: May 24, 2022Publication date: November 30, 2023Applicant: MICRON TECHNOLOGY, INC.Inventors: YUTAKA UEMURA, YOSHIYA KOMATSU
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Publication number: 20230386555Abstract: Apparatuses, systems, and methods for bias temperature instability (BTI) mitigation. A BTI oscillator provides a periodic BTI signal. A BTI logic circuit generates a BTI pulse signal based on the periodic BTI signal and synchronized to a clock signal. A clock gating circuit passes the clock signal to a clock path when the periodic BTI signal is active. When the memory is in an unclocked mode, where an external clock is not received, the periodic BTI signal is provided to a clock input buffer and passed as the clock signal.Type: ApplicationFiled: May 26, 2022Publication date: November 30, 2023Applicant: MICRON TECHNOLOGY, INC.Inventors: YOSHIYA KOMATSU, YUTAKA UEMURA
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Patent number: 11749324Abstract: Disclosed herein is an apparatus that includes a first group including a plurality of first latch circuits coupled in series and a second group including a plurality of second latch circuits coupled in series. Each of the first latch circuits performs a latch operation in synchronization with a rise trigger signal. Each of the second latch circuits performs a latch operation in synchronization with a fall trigger signal. The rise and fall trigger signals are alternately activated every even clock cycles or every odd clock cycles. In response to a division ratio, first one or more of the first and second latch circuits are bypassed and second one or more of the first and second latch circuits are cyclically coupled.Type: GrantFiled: September 23, 2022Date of Patent: September 5, 2023Assignee: Micron Technology, Inc.Inventor: Yutaka Uemura
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Publication number: 20230076261Abstract: Methods, apparatuses, and systems related to coordinating a set of timing-critical operations across parallel processing pipelines are described. The coordination may include selectively using (1) circuitry associated with a corresponding pipeline to generate enable signals associated with the timing critical operations when a separation between the operations corresponds to a number of pipelines or (2) circuitry associated with a non-corresponding or another pipeline when the separation is not a factor of the number of pipelines.Type: ApplicationFiled: September 3, 2021Publication date: March 9, 2023Inventors: Navya Sri Sreeram, Kallol Mazumder, Ryo Fujimaki, Kazutaka Miyano, Yutaka Uemura
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Patent number: 11594265Abstract: Methods, apparatuses, and systems related to coordinating a set of timing-critical operations across parallel processing pipelines are described. The coordination may include selectively using (1) circuitry associated with a corresponding pipeline to generate enable signals associated with the timing critical operations when a separation between the operations corresponds to a number of pipelines or (2) circuitry associated with a non-corresponding or another pipeline when the separation is not a factor of the number of pipelines.Type: GrantFiled: September 3, 2021Date of Patent: February 28, 2023Assignee: Micron Technology, Inc.Inventors: Navya Sri Sreeram, Kallol Mazumder, Ryo Fujimaki, Kazutaka Miyano, Yutaka Uemura
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Publication number: 20230014446Abstract: Disclosed herein is an apparatus that includes a first group including a plurality of first latch circuits coupled in series and a second group including a plurality of second latch circuits coupled in series. Each of the first latch circuits performs a latch operation in synchronization with a rise trigger signal. Each of the second latch circuits performs a latch operation in synchronization with a fall trigger signal. The rise and fall trigger signals are alternately activated every even clock cycles or every odd clock cycles. In response to a division ratio, first one or more of the first and second latch circuits are bypassed and second one or more of the first and second latch circuits are cyclically coupled.Type: ApplicationFiled: September 23, 2022Publication date: January 19, 2023Applicant: MICRON TECHNOLOGY, INC.Inventor: Yutaka Uemura
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Patent number: 11456024Abstract: Disclosed herein is an apparatus that includes a first shift register circuit including a plurality of first latch circuits coupled in series, and a second shift register circuit including a plurality of second latch circuits coupled in series. The first and second shift register circuits are cyclically coupled. Each of the first latch circuits is configured to perform the latch operation in synchronization with a rise edge of a first clock signal. Each of the second latch circuits is configured to perform the latch operation in synchronization with a fall edge of a first clock signal when a first selection signal is in a first state. One or more first latch circuits and one or more second latch circuits are configured to be bypassed when a second selection signal indicates a predetermined value.Type: GrantFiled: September 14, 2020Date of Patent: September 27, 2022Assignee: Micron Technology, Inc.Inventor: Yutaka Uemura
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Publication number: 20220246227Abstract: Disclosed herein is an apparatus that includes first and second shift register circuits coupled in series, the first and second shift register circuits being configured to perform a shift operation of a trigger signal in synchronization with a clock signal, and a clock control circuit configured to set a frequency of the clock signal to a first frequency when the trigger signal is in the first shift register circuit and set a frequency of the clock signal to a second frequency different from the first frequency when the trigger signal is in the second shift register circuit.Type: ApplicationFiled: April 18, 2022Publication date: August 4, 2022Applicant: MICRON TECHNOLOGY, INC.Inventor: Yutaka Uemura
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Patent number: 11309047Abstract: Disclosed herein is an apparatus that includes first and second shift register circuits coupled in series, the first and second shift register circuits being configured to perform a shift operation of a trigger signal in synchronization with a clock signal, and a clock control circuit configured to set a frequency of the clock signal to a first frequency when the trigger signal is in the first shift register circuit and set a frequency of the clock signal to a second frequency different from the first frequency when the trigger signal is in the second shift register circuit.Type: GrantFiled: September 14, 2020Date of Patent: April 19, 2022Assignee: Micron Technology, Inc.Inventor: Yutaka Uemura
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Publication number: 20220084569Abstract: Disclosed herein is an apparatus that includes a first shift register circuit including a plurality of first latch circuits coupled in series, and a second shift register circuit including a plurality of second latch circuits coupled in series. The first and second shift register circuits are cyclically coupled. Each of the first latch circuits is configured to perform the latch operation in synchronization with a rise edge of a first clock signal. Each of the second latch circuits is configured to perform the latch operation in synchronization with a fall edge of a first clock signal when a first selection signal is in a first state. One or more first latch circuits and one or more second latch circuits are configured to be bypassed when a second selection signal indicates a predetermined value.Type: ApplicationFiled: September 14, 2020Publication date: March 17, 2022Applicant: MICRON TECHNOLOGY, INC.Inventor: Yutaka Uemura
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Publication number: 20220084615Abstract: Disclosed herein is an apparatus that includes first and second shift register circuits coupled in series, the first and second shift register circuits being configured to perform a shift operation of a trigger signal in synchronization with a clock signal, and a clock control circuit configured to set a frequency of the clock signal to a first frequency when the trigger signal is in the first shift register circuit and set a frequency of the clock signal to a second frequency different from the first frequency when the trigger signal is in the second shift register circuit.Type: ApplicationFiled: September 14, 2020Publication date: March 17, 2022Applicant: MICRON TECHNOLOGY, INC.Inventor: Yutaka Uemura
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Patent number: 10896716Abstract: Apparatuses and methods for self-refreshing a plurality of dies are described. An example apparatus includes a first die including a first bank and a second bank, the first bank and the second bank including memory cells; and a second die vertically stacked with the first die, the second die including a third bank and a fourth bank, the third bank and the fourth bank including memory cells. The third bank is vertically aligned with the first bank. The first bank and the fourth bank are configured to be refreshed prior to refreshing the second bank and the fourth bank.Type: GrantFiled: September 13, 2019Date of Patent: January 19, 2021Assignee: Micron Technology, Inc.Inventor: Yutaka Uemura
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Patent number: 10872643Abstract: An apparatus may include a first pad and a first input circuit coupled to the first pad. The first input circuitry may include a first signal propagation path that couples to the first pad, a latch circuit, a second signal propagation path that couples to the latch circuit, and a gate circuitry coupling between the first and second signal propagation paths. The first signal propagation path may have first signal propagation time and the second signal propagation path may have second signal propagation time that is greater than the first propagation time.Type: GrantFiled: July 22, 2019Date of Patent: December 22, 2020Assignee: Micron Technology, Inc.Inventors: Yutaka Uemura, Yasuhiro Takai
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Publication number: 20200013452Abstract: Apparatuses and methods for self-refreshing a plurality of dies are described. An example apparatus includes a first die including a first bank and a second bank, the first bank and the second bank including memory cells; and a second die vertically stacked with the first die, the second die including a third bank and a fourth bank, the third bank and the fourth bank including memory cells. The third bank is vertically aligned with the first bank. The first bank and the fourth bank are configured to be refreshed prior to refreshing the second bank and the fourth bank.Type: ApplicationFiled: September 13, 2019Publication date: January 9, 2020Applicant: Micron Technology, Inc.Inventor: Yutaka Uemura
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Publication number: 20190371374Abstract: An apparatus may include a first pad and a first input circuit coupled to the first pad. The first input circuitry may include a first signal propagation path that couples to the first pad, a latch circuit, a second signal propagation path that couples to the latch circuit, and a gate circuitry coupling between the first and second signal propagation paths. The first signal propagation path may have first signal propagation time and the second signal propagation path may have second signal propagation time that is greater than the first propagation time.Type: ApplicationFiled: July 22, 2019Publication date: December 5, 2019Inventors: Yutaka Uemura, Yasuhiro Takai
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Patent number: 10424363Abstract: Apparatuses and methods for self-refreshing a plurality of dies are described. An example apparatus includes a first die including a first bank and a second bank, the first bank and the second bank including memory cells; and a second die vertically slacked with the first die, the second die including a third bank and a fourth bank, the third bank and the fourth bank including memory cells. The third bank is vertically aligned with the first bank. The first bank and the fourth bank are configured to be refreshed prior to refreshing the second bank and the fourth bank.Type: GrantFiled: July 3, 2018Date of Patent: September 24, 2019Assignee: Micron Technology, Inc.Inventor: Yutaka Uemura
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Patent number: 10403335Abstract: An apparatus may include a first pad and a first input circuit coupled to the first pad. The first input circuitry may include a first signal propagation path that couples to the first pad, a latch circuit, a second signal propagation path that couples to the latch circuit, and a gate circuitry coupling between the first and second signal propagation paths. The first signal propagation path may have first signal propagation time and the second signal propagation path may have second signal propagation time that is greater than the first propagation time.Type: GrantFiled: June 4, 2018Date of Patent: September 3, 2019Assignee: Micron Technology, Inc.Inventors: Yutaka Uemura, Yasuhiro Takai