Abstract: Apparatuses and methods for self-refreshing a plurality of dies are described. An example apparatus includes a first die including a first bank and a second bank, the first bank and the second bank including memory cells; and a second die vertically slacked with the first die, the second die including a third bank and a fourth bank, the third bank and the fourth bank including memory cells. The third bank is vertically aligned with the first bank. The first bank and the fourth bank are configured to be refreshed prior to refreshing the second bank and the fourth bank.

Abstract: Apparatuses and methods for self-refreshing a plurality of dies are described. An example apparatus includes a first die including a first bank and a second bank, the first bank and the second bank including memory cells; and a second die vertically stacked with the first die, the second die including a third bank and a fourth bank, the third bank and the fourth bank including memory cells. The third bank is vertically aligned with the first bank. The first bank and the fourth bank are configured to be refreshed prior to refreshing the second bank and the fourth bank.

Abstract: Disclosed herein is a device that includes a coarse adjusting circuit generating first and second clock signals having different phases from each other, and a fine adjusting circuit generating a third clock signal having a phase between a phase of the first clock signal and a phase of the second clock signal. The fine adjusting circuit includes a plurality of first transistors receiving the first clock signal and a plurality of second transistors receiving the second clock signal. The fine adjusting circuit controls the phase of the third clock signal by synthesizing the first clock signal output from selected zero or more of the first transistors based on adjustment codes and the second clock signal output from selected zero or more of the second transistors based on the adjustment codes. The adjustment codes are not a binary system.

Abstract: Disclosed herein is a device that includes a coarse adjusting circuit generating first and second clock signals having different phases from each other, and a fine adjusting circuit generating a third clock signal having a phase between a phase of the first clock signal and a phase of the second clock signal. The fine adjusting circuit includes a plurality of first transistors receiving the first clock signal and a plurality of second transistors receiving the second clock signal. The fine adjusting circuit controls the phase of the third clock signal by synthesizing the first clock signal output from selected zero or more of the first transistors based on adjustment codes and the second clock signal output from selected zero or more of the second transistors based on the adjustment codes. The adjustment codes are not a binary system.

Abstract: An optical disk having both CLV and CAV control regions is recorded by a recording system that allows moving from CLV control to CAV control without interrupting the data stream. The switching is accomplished by a switching device selecting between the output of a CAV control signal generator that is equipped with a divider which sets a certain number of frames or sectors for each single rotation of the disk and the output of a CLV control signal generator, a detector that detects whether the frequency and phase of the output of the signal generator of the drive motor and the control signal not selected by the switching device match, and the output of this detection means.

Abstract: An optical disk having both CLV and CAV control regions is recorded by a recording system that allows moving from CLV control to CAV control without interrupting the data stream. The switching is accomplished by a switching device selecting between the output of a CAV control signal generator that is equipped with a divider which sets a certain number of frames or sectors for each single rotation of the disk and the output of a CLV control signal generator, a detector that detects whether the frequency and phase of the output of the signal generator of the drive motor and the control signal not selected by the switching device match, and the output of this detection means.

Abstract: An optical disk having both CLV and CAV control regions is recorded by a recording system that allows moving from CLV control to CAV control without interrupting the data stream. The switching is accomplished by a switching device selecting between the output of a CAV control signal generator that is equipped with a divider which sets a certain number of frames or sectors for each single rotation of the disk and the output of a CLV control signal generator, a detector that detects whether the frequency and phase of the output of the signal generator of the drive motor and the control signal not selected by the switching device match, and the output of this detection means.