Abstract: A semiconductor device and methods of forming the same. In some embodiments, a method for forming a semiconductor device includes forming a redistribution layer that includes connecting vias and a surface mount pad via and the top surface width of each via is larger than a bottom surface width. The method includes connecting a component to the redistribution layer by a plurality of ?-bumps and filling a gap between the component and the redistribution layer with a mold and an underfill. The method includes etching back the redistribution layer to expose the surface mount pad via and attaching a surface mount pad to the surface mount pad via. The surface mount pad is connected to the bottom surface width of the surface mount pad via and the surface mount pad includes a protrude. The method includes connecting a device to a bottom surface of the surface mount pad.

Abstract: A biobased water repellent auxiliary agent and a method of manufacturing the same are provided. The biobased water repellent auxiliary agent includes a molecular complex composed of a polyurethane (PU) dendrimer and a water-based polyurethane dispersion (PUD). The PU dendrimer is formed by polymerizing a trifunctional-group-containing biobased material and an aliphatic linear isocyanate. The water-based PUD includes a monomer derived from the trifunctional-group-containing biobased material, a monomer derived from a cyclic isocyanate, and a monomer derived from a hydrophilic compound. The molecular complex is formed by copolymerizing the PU dendrimer, the trifunctional-group-containing biobased material, the cyclic isocyanate, and the hydrophilic compound.

Abstract: Providing are a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a substrate, a first isolation structure, a second isolation structure, a word line, a pad layer, a cover layer and a dummy pattern. The substrate has a memory device region and a peripheral region. The first isolation structure is disposed in the substrate in the memory device region to define an active area. The second isolation structure is disposed in the substrate in the peripheral region. The word line is disposed in the substrate in the active area. The pad layer is disposed on the substrate in the memory device region. The cover layer is disposed on the pad layer and extends downward to the top surface of the word line. The dummy pattern is disposed in the second isolation structure.

Abstract: A baby electrode patch is connected to an electrocardiogram measurement equipment to measure an electrocardiogram of a baby. The baby electrode patch included an electrode patch main body, an electrode patch extension portion, and an electrode patch connection portion. The electrode patch main body is equipped with a plurality of main body electrodes. The electrode patch extension portion is connected to the electrode patch main body, and the electrode patch connection portion is connected to the electrode patch extension portion. The electrode patch extension portion extends from the electrode patch main body towards a side of the baby so as to allow the electrocardiogram measurement equipment to be placed at the side of the baby.

Abstract: An electrocardiogram display method includes the following steps. First, the electrocardiogram is measured, the ST amplitudes of multiple electrocardiogram leads are then calculated based on the measured electrocardiogram, the measured electrocardiograms are classified according to regions of the heart, and bar charts of the ST amplitudes of the electrocardiogram leads are drawn according to the region classification.

Abstract: A stator for an axial flux machine includes a plurality of units (100; 200; 400) disposed generally circumferentially around an axis. Each of the units (100; 200; 400) is operable to generate a magnetic field generally parallel to the axis. Each of the units (100; 200; 400) respectively includes: an axially extending stator core tooth (102T; 202T; 402T) defining at least part of a stator core, and a set of windings (102C; 202C; 402C) wound around the stator core tooth. The stator includes a heat dissipation arrangement for facilitating dissipation of heat from the stator core during operation of the stator. By facilitating dissipation of heat generated or accumulated in the stator core during operation of the stator, the performance, efficiency and/or lifespan of the stator can be improved.

Abstract: The invention is related to a method, performed by a processing unit, includes: obtaining a group number and a section number associated with a logical address carried in a host read command; determining whether a variable corresponding to a first mode is lower than or equal to an accumulation threshold; performing operations of the first mode for reading first records associated with the group number and the section number from a host-address to flash-address mapping (H2F) table in a flash module, and second records being located after the first records, and storing them in a random access memory (RAM) when the variable is lower than or equal to the accumulation threshold; performing operations of a second mode for reading the first records from the H2F table in the flash module only, and storing them in the RAM when the variable is higher than the accumulation threshold.

Abstract: Some implementations described herein provide for techniques to form a biased backside deep trench isolation and grid structure for a backside illumination image sensor. The techniques include forming an array of backside deep trench isolation structures and a biasing-pad that electrically connects to the array of metal-filled backside deep trench isolation structures through the grid structure. The array of backside deep trench isolation structures, the grid structure, and the biasing-pad structure may reduce a likelihood of electrical cross-talk and/or oblique light cross-talk between the photodiodes of the backside illumination image sensor. In this way, a performance of the backside illumination image sensor may be improved. Such improvements may include a suppression of a dark current within the backside illumination image sensor, a reduction in a number of white pixels, and a reduction in cross-talk within the backside illumination image sensor.

Abstract: An electronic device is provided. The electronic device includes a display panel and a cover lens. The display panel has an active area. The cover lens is disposed corresponding to the display panel. The cover lens includes a substrate, a first alignment mark, and a second alignment mark. The first alignment mark is disposed on a surface of the substrate and corresponds to a first position in the active area. The second alignment mark is disposed on the surface of the substrate and corresponds to a second position in the active area. The second position differs from the first position. Wherein, a transmittance of the first alignment mark in a first alignment region is 20% to 99%.

Abstract: A resistive memory apparatus including a memory cell array, at least one dummy transistor and a control circuit is provided. The memory cell array includes a plurality of memory cells. Each of the memory cells includes a resistive switching element. The dummy transistor is electrically isolated from the resistive switching element. The control circuit is coupled to the memory cell array and the dummy transistor. The control circuit is configured to provide a first bit line voltage, a source line voltage and a word line voltage to the dummy transistor to drive the dummy transistor to output a saturation current. The control circuit is further configured to determine a value of a second bit line voltage for driving the memory cells according to the saturation current. In addition, an operating method and a memory cell array of the resistive memory apparatus are also provided.

Abstract: A pellicle membrane is formed from a core layer and two capping layers of specified structure. In some embodiments, the core layer includes a high percentage of the Mo3Si crystal phase. In other embodiments, the capping layers comprise silicon oxynitride or silicon carbon nitride. The resulting pellicle membrane has a combination of high transmittance for EUV light and low reflectivity of both EUV and DUV light.

Abstract: An electronic device includes a display panel and a cover plate disposed relative to the display panel. The display panel has a display area and a peripheral area adjacent to the display area. The cover plate includes a substrate. The cover plate includes a light-shielding structure disposed on the surface of the substrate. The light-shielding structure includes a first portion corresponding to the display area. The cover plate includes an anti-reflective layer disposed on another surface of the substrate. The anti-reflective layer corresponds to the display area and the peripheral area. The penetration rate of the portion of the cover plate that corresponds to the display area is in a range of 20% to 92%.

Abstract: A method for performing a test upon a flash memory module includes: performing data writing upon a plurality of first blocks of a first group in the flash memory module; reading the plurality of first blocks of the first group to determine whether there is any abnormal block in the plurality of first blocks and generating a first test result; after the plurality of first blocks are read, performing data writing upon a plurality of second blocks of a second group in the flash memory module; and reading the plurality of second blocks of the second group to determine whether there is any abnormal block in the plurality of second blocks and generating a second test result.

Abstract: A battery cell pressing system may include a sealed case having an internal chamber, the sealed case including at least one window to allow visual inspection of the internal chamber; a pouch-type battery cell disposed within the internal chamber of the sealed case; a fluid filling the internal chamber and surrounding the pouch-type battery cell; a fluid entrance in fluid communication with the internal chamber; a pressing member configured to adjust a pressure of the fluid within the internal chamber such that the pressure at which the fluid presses the pouch-type battery cell is approximately 1 MPa to 10 MPa; a heater configured to heat the fluid within the internal chamber; and a pressure measuring member configured to measure the pressure within the internal chamber. The fluid isotropically presses the pouch-type battery cell during at least one of charging and discharging of the pouch-type battery cell.

Abstract: A method of controlling a cycling pressure of a secondary battery can include assembling the secondary battery by stacking a cathode, a separator, and an anode in order; activating the secondary battery by applying a pressure of about 5 MPa or less; and cycling the secondary battery by applying the pressure of about 5 MPa or less.

Abstract: An electronic device is provided. The electronic device includes a panel, a protective substrate, and a first light-shielding structure. The panel has an active area and a peripheral area. The peripheral area is adjacent to the active area. The protective substrate is disposed opposite to the panel. The first light-shielding structure is disposed on a surface of the protective substrate and corresponds to the peripheral area. A portion of the first light-shielding structure that overlaps the peripheral area has at least one opening.

Abstract: Various embodiments include protection layers for a transistor and methods of forming the same. In an embodiment, a method includes: exposing a semiconductor nanostructure, a dummy nanostructure, and an isolation region by removing a dummy gate; increasing a deposition selectivity between a top surface of the semiconductor nanostructure and a top surface of the isolation region relative a selective deposition process; depositing a protection layer on the top surface of the isolation region by performing the selective deposition process; removing the dummy nanostructure by selectively etching a dummy material of the dummy nanostructure at a faster rate than a protection material of the protection layer; and forming a gate structure around the semiconductor nanostructure.

Abstract: A method of fabricating a semiconductor device includes the following steps. A plurality of doped regions are formed in a substrate. A first dielectric layer is formed on the substrate. A plurality of first contacts and second contacts are formed in the first dielectric layer to be connected to the plurality of doped regions. A memory element is formed on the first dielectric layer. The memory element is electrically connected to the second contact. A second dielectric layer is formed on the first dielectric layer. The second dielectric layer surrounds the memory element. A conductive line is formed in the second dielectric layer. A top surface of the conductive line is at a same level as a top surface of the memory element, and the conductive line is electrically connected to the plurality of first contacts.

Abstract: Methods for recovering the performance of a halide-based solid electrolyte are described. In one aspect, a halide-based solid electrolyte that has been exposed to air is subjected to a heat-treatment process, where the performance of the halide-based solid electrolyte is recovered, e.g., the ionic conductivity obtained after heat treatment is recovered to a level similar to that before air exposure.

Abstract: A power semiconductor device includes a semiconductor substrate, a drift layer, a well region, a doped region, two dummy trenches, a gate structure and a dielectric layer. The semiconductor substrate is doped to have a first conductive channel. The drift layer on the semiconductor substrate is doped to have the first conductive channel. The well region on the drift layer is doped to have a second conductive channel having a polarity opposite to that of the first conductive channel. The doped region on the well region is doped to have the first conductive channel. Two dummy trenches pass through the doped region and the well region. Each of the dummy trenches has a dummy gate. The gate structure has a real gate and is between the dummy trenches. The dielectric layer isolates the dummy gate and the real gate from the doped region, the well region and the drift layer.