Abstract: In an example, a memory device includes a first stack structure and a second stack structure over the first stack structure. Each of the first stack structure and the second stack structure includes alternately stacked conductor layers and first insulating layers. The memory device also includes a first channel structure extending through the first stack structure, and a second channel structure extending through the second stack structure and connected with the first channel structure. A width of an end of the first channel structure closer to the second channel structure is greater than that of the second channel structure closer to the first channel structure. The memory device further includes a pillar structure extending through the first stack structure and the second stack structure. The pillar structure includes a metal layer.

Abstract: A memory device includes a stack including conductive layers and insulating layers alternatingly stacked in a first direction, a semiconductor channel extending through the stack in the first direction, and a staircase structure including sub-staircase structures in a second direction perpendicular to the first direction. One of the sub-staircase structures includes two portions arranged along the second direction. Each of the portions includes first staircases arranged in the second direction and second staircases arranged in a third direction perpendicular to the first direction and the second direction.

Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the disclosed method comprises forming a plurality of dielectric stacks stacked on one another over a substrate to create a multiple-stack staircase structure. Each one of the plurality of dielectric stacks comprises a plurality of dielectric pairs arranged along a direction perpendicular to a top surface of the substrate. The method further comprises forming a filling structure that surrounds the multiple-stack staircase structure, forming a semiconductor channel extending through the multiple-staircase structure, wherein the semiconductor channel comprises unaligned sidewall surfaces, and forming a supporting pillar extending through at least one of the multiple-staircase structure and the filling structure, wherein the supporting pillar comprises aligned sidewall surfaces.

Abstract: A method for forming a staircase structure of 3D memory, including: forming an alternating layer stack comprising a plurality of dielectric layer pairs disposed over a substrate; forming a first mask stack over the alternating layer stack; patterning the first mask stack to define a staircase region comprising a number of N sub-staircase regions over the alternating layer stack using a lithography process and N is greater than 1; forming a first staircase structure over the staircase region, the first staircase structure has a number of M steps at each of the staircase regions and M is greater than 1; and forming a second staircase structure on the first staircase structure, the second staircase structure has a number of 2*N*M steps at the staircase region.

Abstract: A method for forming a staircase structure of 3D memory, including: forming an alternating layer stack comprising a plurality of dielectric layer pairs disposed over a substrate; forming a first mask stack over the alternating layer stack; patterning the first mask stack to define a staircase region comprising a number of N sub-staircase regions over the alternating layer stack using a lithography process and N is greater than 1; forming a first staircase structure over the staircase region, the first staircase structure has a number of M steps at each of the staircase regions and M is greater than 1; and forming a second staircase structure on the first staircase structure, the second staircase structure has a number of 2*N*M steps at the staircase region.

Abstract: A method for forming a staircase structure of 3D memory, including: forming an alternating layer stack comprising a plurality of dielectric layer pairs disposed over a substrate; forming a first mask stack over the alternating layer stack; patterning the first mask stack to define a staircase region comprising a number of N sub-staircase regions over the alternating layer stack using a lithography process and N is greater than 1; forming a first staircase structure over the staircase region, the first staircase structure has a number of M steps at each of the staircase regions and M is greater than 1; and forming a second staircase structure on the first staircase structure, the second staircase structure has a number of 2*N*M steps at the staircase region.

Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device includes a substrate having one or more first recesses in a first region and one or more second recesses in a second region. A liner layer is disposed over the sidewalls and bottom of the one or more first recesses in the first region and an epitaxially-grown material is formed in the one or more second recesses in the second region. One or more NAND strings are formed over the epitaxially-grown material disposed in the one or more second recesses, and one or more vertical structures are formed over the one or more first recesses in the first region.

Abstract: A method for forming a staircase structure of 3D memory, including: forming an alternating layer stack comprising a plurality of dielectric layer pairs disposed over a substrate; forming a first mask stack over the alternating layer stack; patterning the first mask stack to define a staircase region comprising a number of N sub-staircase regions over the alternating layer stack using a lithography process and N is greater than 1; forming a first staircase structure over the staircase region, the first staircase structure has a number of M steps at each of the staircase regions and M is greater than 1; and forming a second staircase structure on the first staircase structure, the second staircase structure has a number of 2*N*M steps at the staircase region.

Abstract: Embodiments of three-dimensional (3D) memory devices having a memory layer that confines electron transportation and methods for forming the same are disclosed. The 3D memory device can include a structure of a plurality of gate electrodes insulated by a sealing structure over a substrate. The sealing structure can include an airgap between adjacent gate electrodes along a direction perpendicular to a top surface of the substrate. The 3D memory device can also include a semiconductor channel extending from a top surface of the structure to the substrate. The semiconductor channel can include a memory layer that has two portions extending along different directions. The 3D memory device can further include a source structure extending from the top surface of the structure to the substrate and between adjacent gate electrodes along a direction parallel to the top surface the substrate.

Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device includes a substrate having one or more first recesses in a first region and one or more second recesses in a second region. A liner layer is disposed over the sidewalls and bottom of the one or more first recesses in the first region and an epitaxially-grown material is formed in the one or more second recesses in the second region. One or more NAND strings are formed over the epitaxially-grown material disposed in the one or more second recesses, and one or more vertical structures are formed over the one or more first recesses in the first region.

Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device includes a substrate having one or more first recesses in a first region and one or more second recesses in a second region. A liner layer is disposed over the sidewalls and bottom of the one or more first recesses in the first region and an epitaxially-grown material is formed in the one or more second recesses in the second region. One or more NAND strings are formed over the epitaxially-grown material disposed in the one or more second recesses, and one or more vertical structures are formed over the one or more first recesses in the first region.

Abstract: A method for forming a staircase structure of 3D memory, including: forming an alternating layer stack comprising a plurality of dielectric layer pairs disposed over a substrate; forming a first mask stack over the alternating layer stack; patterning the first mask stack to define a staircase region comprising a number of N sub-staircase regions over the alternating layer stack using a lithography process and N is greater than 1; forming a first staircase structure over the staircase region, the first staircase structure has a number of M steps at each of the staircase regions and M is greater than 1; and forming a second staircase structure on the first staircase structure, the second staircase structure has a number of 2*N*M steps at the staircase region.

Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device includes a substrate having one or more first recesses in a first region and one or more second recesses in a second region. A liner layer is disposed over the sidewalls and bottom of the one or more first recesses in the first region and an epitaxially-grown material is formed in the one or more second recesses in the second region. One or more NAND strings are formed over the epitaxially-grown material disposed in the one or more second recesses, and one or more vertical structures are formed over the one or more first recesses in the first region.

Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device includes a substrate having one or more first recesses in a first region and one or more second recesses in a second region. A liner layer is disposed over the sidewalls and bottom of the one or more first recesses in the first region and an epitaxially-grown material is formed in the one or more second recesses in the second region. One or more NAND strings are formed over the epitaxially-grown material disposed in the one or more second recesses, and one or more vertical structures are formed over the one or more first recesses in the first region.

Abstract: Embodiments of three-dimensional (3D) memory devices having a memory layer that confines electron transportation and methods for forming the same are disclosed. The 3D memory device can include a structure of a plurality of gate electrodes insulated by a sealing structure over a substrate. The sealing structure can include an airgap between adjacent gate electrodes along a direction perpendicular to a top surface of the substrate. The 3D memory device can also include a semiconductor channel extending from a top surface of the structure to the substrate. The semiconductor channel can include a memory layer that has two portions extending along different directions. The 3D memory device can further include a source structure extending from the top surface of the structure to the substrate and between adjacent gate electrodes along a direction parallel to the top surface the substrate.

Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device includes a substrate having one or more first recesses in a first region and one or more second recesses in a second region. A liner layer is disposed over the sidewalls and bottom of the one or more first recesses in the first region and an epitaxially-grown material is formed in the one or more second recesses in the second region. One or more NAND strings are formed over the epitaxially-grown material disposed in the one or more second recesses, and one or more vertical structures are formed over the one or more first recesses in the first region.

Abstract: A method for forming a staircase structure of 3D memory, including: forming an alternating layer stack comprising a plurality of dielectric layer pairs disposed over a substrate; forming a first mask stack over the alternating layer stack; patterning the first mask stack to define a staircase region comprising a number of N sub-staircase regions over the alternating layer stack using a lithography process and N is greater than 1; forming a first staircase structure over the staircase region, the first staircase structure has a number of M steps at each of the staircase regions and M is greater than 1; and forming a second staircase structure on the first staircase structure, the second staircase structure has a number of 2*N*M steps at the staircase region.

Abstract: Embodiments of interconnect structures of a three-dimensional (3D) memory device and method for forming the interconnect structures are disclosed. In an example, a 3D NAND memory device includes a semiconductor substrate, an alternating layer stack disposed on the semiconductor substrate, and a dielectric structure, which extends vertically through the alternating layer stack, on an isolation region of the substrate. Further, the alternating layer stack abuts a sidewall surface of the dielectric structure and the dielectric structure is formed of a dielectric material. The 3D memory device additionally includes one or more through array contacts that extend vertically through the dielectric structure and the isolation region, and one or more channel structures that extend vertically through the alternating layer stack.

Abstract: Disclosed is a method for forming a staircase structure of 3D memory devices, comprising (i) forming a stack of layers on a substrate; (ii) removing a portion of the stack to form a lower region and a upper region; (iii) forming a mask to cover the lower region and the upper region of the stack; (iv) forming a first opening in the mask to expose a first portion of the stack in the lower region and a second opening in the mask to expose a second portion of the stack in the upper region; (v) forming a photoresist layer to cover the stack and the mask; (vi) using a same set of trim-etch processes to pattern the photoresist layer to form a set of staircases in the first opening and the second opening; (vii) removing the photoresist layer and the mask; and repeating (iii), (iv), (v), (vi) and (vii) sequentially.

Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the disclosed method comprises forming a plurality of dielectric stacks stacked on one another over a substrate to create a multiple-stack staircase structure. Each one of the plurality of dielectric stacks comprises a plurality of dielectric pairs arranged along a direction perpendicular to a top surface of the substrate. The method further comprises forming a filling structure that surrounds the multiple-stack staircase structure, forming a semiconductor channel extending through the multiple-staircase structure, wherein the semiconductor channel comprises unaligned sidewall surfaces, and forming a supporting pillar extending through at least one of the multiple-staircase structure and the filling structure, wherein the supporting pillar comprises aligned sidewall surfaces.