Patents by Inventor Yuui Shimizu
Yuui Shimizu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20110215836Abstract: According to one embodiment, a clamp transistor is inserted in series between a P-channel field effect transistor and an N-channel field effect transistor and an intermediate level between a high potential supplied to a source of the P-channel field effect transistor and a low potential supplied to a source of the N-channel field effect transistor is input into a gate of the clamp transistor to clamp a drain potential of the N-channel field effect transistor.Type: ApplicationFiled: March 4, 2011Publication date: September 8, 2011Applicant: Kabushiki Kaisha ToshibaInventor: Yuui SHIMIZU
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Patent number: 7965555Abstract: A non-volatile semiconductor memory device including: a NAND string having multiple memory cells connected in series and first and second select gate transistors disposed on the both ends; word lines coupled to the memory cells; and first and second select gate lines coupled to the first and second select gate transistors, wherein a data read mode is defined by the following bias condition: a selected word line is applied with a read voltage; one adjacent to the selected word line within first unselected word lines disposed on the first select gate line side is applied with a first read pass voltage while the others are applied with a second read pass voltage lower than the first read pass voltage; and second unselected word lines disposed on the second select gate line side are applied with a third read pass voltage higher than the first read voltage.Type: GrantFiled: February 2, 2009Date of Patent: June 21, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Yuko Namiki, Takuya Futatsuyama, Yuui Shimizu
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Publication number: 20110128768Abstract: According to one embodiment, a differential circuit receives, as differential inputs, a readout signal read out from a semiconductor storage element and a reference voltage. An equalizing circuit controls, taking into account a state of a past input signal output from the differential circuit, the potential of the present differential signal output from the differential circuit. A sense amplifier detects a state of the differential signal output from the equalizing circuit. A state holding circuit holds a past state of the differential signal detected by the sense amplifier and supplies the state to the equalizing circuit.Type: ApplicationFiled: September 17, 2010Publication date: June 2, 2011Applicant: Kabushiki Kaisha ToshibaInventor: Yuui SHIMIZU
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Publication number: 20110074494Abstract: A semiconductor device, a semiconductor memory tester, and a multi-chip package are provided. The semiconductor device includes a plurality of nonvolatile semiconductor memories; a boosting circuit which generates a boosted voltage for operating the plurality of nonvolatile semiconductor memories; and a boosting circuit controller which controls the operation of the boosting circuit to generate the boosted voltage on the basis of an operation sequence of the plurality of nonvolatile semiconductor memories.Type: ApplicationFiled: December 8, 2010Publication date: March 31, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yuui Shimizu, Shigeo Ohshima, Mie Matsuo
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Patent number: 7907446Abstract: This disclosure concerns a memory including cell blocks, wherein in a first write sequence for writing data to a first cell block, drivers write the data only to memory cells arranged in a form of a checkered flag among the memory cells included in the first cell block, in a second write sequence for writing the data from the first cell block to a second cell block, the drivers write the data to all memory cells connected to a word line selected in the second cell block, and when the data is read from the first cell block or at a time of data verification when data is written to the first cell block, the word line drivers simultaneously apply a read voltage to two adjacent word lines, and the sense amplifiers detects the data in the memory cells connected to the two word lines.Type: GrantFiled: November 7, 2008Date of Patent: March 15, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Yuui Shimizu, Toshiaki Edahiro
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Patent number: 7869265Abstract: A magnetic random access memory includes a first interconnection extending to a first direction, a second interconnection extending to a second direction perpendicular to the first direction, a magnetoresistive effect element formed between the first and second interconnections, having one terminal connected to the first interconnection, includes a fixed layer, a recording layer and a nonmagnetic layer, a film thickness of the fixed layer being larger than that of the recording layer, and a width of the fixed layer being larger than that of the recording layer, and configured to reverse a magnetization direction in the recording layer by supplying a first electric current between the fixed layer and the recording layer, and a diode having one terminal connected to the other terminal of the magnetoresistive effect element, and the other terminal connected to the second interconnection, and configured to supply the first electric current in only one direction.Type: GrantFiled: February 5, 2008Date of Patent: January 11, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Yuui Shimizu, Tatsuya Kishi
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Patent number: 7869240Abstract: A semiconductor device, a semiconductor memory tester, and a multi-chip package are provided. The semiconductor device includes a plurality of nonvolatile semiconductor memories; a boosting circuit which generates a boosted voltage for operating the plurality of nonvolatile semiconductor memories; and a boosting circuit controller which controls the operation of the boosting circuit to generate the boosted voltage on the basis of an operation sequence of the plurality of nonvolatile semiconductor memories.Type: GrantFiled: June 19, 2008Date of Patent: January 11, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Yuui Shimizu, Shigeo Ohshima, Mie Matsuo
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Patent number: 7864563Abstract: A magnetic random access memory according to an example of the invention comprises a first reference bit line shared by first reference cells, a second reference bit line shared by second reference cells, a first driver-sinker to feed a first writing current, a second driver-sinker to feed a second writing current, and a control circuit which checks data stored in the first and second reference cells line by line, and executes writing simultaneously to all of the first and second reference cells by a uniaxial writing when the data is broken.Type: GrantFiled: September 28, 2007Date of Patent: January 4, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Yuui Shimizu, Tsuneo Inaba
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Patent number: 7859881Abstract: A magnetic memory device includes a first magnetic line which has a plurality of cells made of magnetic domains partitioned by domain walls, and in which information is recorded in each cell, a first write element formed at one end portion of the first magnetic line, and a first read element formed at the other end portion of the first magnetic line.Type: GrantFiled: February 7, 2007Date of Patent: December 28, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Yoshihisa Iwata, Katsuyuki Fujita, Yuui Shimizu
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Patent number: 7835210Abstract: A magnetic random access memory includes a memory element having a first fixed layer, a first recording layer, and a first nonmagnetic layer, a first reference element having a second fixed layer, a second recording layer, and a second nonmagnetic layer, antiparallel data being written in the first reference element, a second reference element making a pair with the first reference element, and having a third fixed layer, a third recording layer, and a third nonmagnetic layer, parallel data being written in the second reference element, and a current source which, when a read operation is performed, supplies a current from the second fixed layer to the second recording layer in the first reference element, and supplies the current from the third recording layer to the third fixed layer in the second reference element.Type: GrantFiled: August 29, 2007Date of Patent: November 16, 2010Assignee: Kabushiki Kaisha ToshibaInventor: Yuui Shimizu
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Patent number: 7791919Abstract: A semiconductor memory device is configured to vertically stack a plurality of memory chips using a resistance-change memory element as a memory cell in one package. The memory chips each have first and second memory position detection pads connected via chip top and bottom electrodes facing each other. Of the vertically stacked memory chips, the lowermost memory chip is provided with the connected chip bottom electrodes of the first and second memory position detection pads. The memory chips each control the variable resistance element, and in a state that the first memory position detection pad has a higher resistance than the second memory position detection pad, compare a voltage applied to the first memory position detection pad with the chip position detection signal using the comparator when a voltage is applied between the first and second memory position detection pads provided on the uppermost layer memory chip.Type: GrantFiled: November 13, 2008Date of Patent: September 7, 2010Assignee: Kabushiki Kaisha ToshibaInventor: Yuui Shimizu
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Publication number: 20090238003Abstract: A non-volatile semiconductor memory device including: a NAND string having multiple memory cells connected in series and first and second select gate transistors disposed on the both ends; word lines coupled to the memory cells; and first and second select gate lines coupled to the first and second select gate transistors, wherein a data read mode is defined by the following bias condition: a selected word line is applied with a read voltage; one adjacent to the selected word line within first unselected word lines disposed on the first select gate line side is applied with a first read pass voltage while the others are applied with a second read pass voltage lower than the first read pass voltage; and second unselected word lines disposed on the second select gate line side are applied with a third read pass voltage higher than the first read voltage.Type: ApplicationFiled: February 2, 2009Publication date: September 24, 2009Applicant: Kabushiki Kaisha ToshibaInventors: Yuko NAMIKI, Takuya Futatsuyama, Yuui Shimizu
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Publication number: 20090135638Abstract: A semiconductor memory device is configured to vertically stack a plurality of memory chips using a resistance-change memory element as a memory cell in one package. The memory chips each have first and second memory position detection pads connected via chip top and bottom electrodes facing each other. Of the vertically stacked memory chips, the lowermost memory chip is provided with the connected chip bottom electrodes of the first and second memory position detection pads. The memory chips each control the variable resistance element, and in a state that the first memory position detection pad has a higher resistance than the second memory position detection pad, compare a voltage applied to the first memory position detection pad with the chip position detection signal using the comparator when a voltage is applied between the first and second memory position detection pads provided on the uppermost layer memory chip.Type: ApplicationFiled: November 13, 2008Publication date: May 28, 2009Inventor: Yuui Shimizu
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Publication number: 20090122611Abstract: This disclosure concerns a memory including cell blocks, wherein in a first write sequence for writing data to a first cell block, drivers write the data only to memory cells arranged in a form of a checkered flag among the memory cells included in the first cell block, in a second write sequence for writing the data from the first cell block to a second cell block, the drivers write the data to all memory cells connected to a word line selected in the second cell block, and when the data is read from the first cell block or at a time of data verification when data is written to the first cell block, the word line drivers simultaneously apply a read voltage to two adjacent word lines, and the sense amplifiers detects the data in the memory cells connected to the two word lines.Type: ApplicationFiled: November 7, 2008Publication date: May 14, 2009Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yuui SHIMIZU, Toshiaki EDAHIRO
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Publication number: 20090067212Abstract: A magnetic random access memory includes a memory element having a first fixed layer, a first recording layer, and a first nonmagnetic layer, a first reference element having a second fixed layer, a second recording layer, and a second nonmagnetic layer, antiparallel data being written in the first reference element, a second reference element making a pair with the first reference element, and having a third fixed layer, a third recording layer, and a third nonmagnetic layer, parallel data being written in the second reference element, and a current source which, when a read operation is performed, supplies a current from the second fixed layer to the second recording layer in the first reference element, and supplies the current from the third recording layer to the third fixed layer in the second reference element.Type: ApplicationFiled: August 29, 2007Publication date: March 12, 2009Inventor: Yuui SHIMIZU
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Publication number: 20090003103Abstract: A semiconductor device, a semiconductor memory tester, and a multi-chip package are provided. The semiconductor device includes a plurality of nonvolatile semiconductor memories; a boosting circuit which generates a boosted voltage for operating the plurality of nonvolatile semiconductor memories; and a boosting circuit controller which controls the operation of the boosting circuit to generate the boosted voltage on the basis of an operation sequence of the plurality of nonvolatile semiconductor memories.Type: ApplicationFiled: June 19, 2008Publication date: January 1, 2009Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yuui SHIMIZU, Shigeo Ohshima, Mie Matsuo
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Publication number: 20080253173Abstract: A magnetic random access memory according to an example of the invention comprises a first reference bit line shared by first reference cells, a second reference bit line shared by second reference cells, a first driver-sinker to feed a first writing current, a second driver-sinker to feed a second writing current, and a control circuit which checks data stored in the first and second reference cells line by line, and executes writing simultaneously to all of the first and second reference cells by a uniaxial writing when the data is broken.Type: ApplicationFiled: September 28, 2007Publication date: October 16, 2008Inventors: Yuui SHIMIZU, Tsuneo INABA
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Publication number: 20080186759Abstract: A magnetic random access memory includes a first interconnection extending to a first direction, a second interconnection extending to a second direction perpendicular to the first direction, a magnetoresistive effect element formed between the first and second interconnections, having one terminal connected to the first interconnection, includes a fixed layer, a recording layer and a nonmagnetic layer, a film thickness of the fixed layer being larger than that of the recording layer, and a width of the fixed layer being larger than that of the recording layer, and configured to reverse a magnetization direction in the recording layer by supplying a first electric current between the fixed layer and the recording layer, and a diode having one terminal connected to the other terminal of the magnetoresistive effect element, and the other terminal connected to the second interconnection, and configured to supply the first electric current in only one direction.Type: ApplicationFiled: February 5, 2008Publication date: August 7, 2008Inventors: Yuui SHIMIZU, Tatsuya Kishi
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Publication number: 20080080234Abstract: A magnetic memory device includes a first magnetic line which has a plurality of cells made of magnetic domains partitioned by domain walls, and in which information is recorded in each cell, a first write element formed at one end portion of the first magnetic line, and a first read element formed at the other end portion of the first magnetic line.Type: ApplicationFiled: February 7, 2007Publication date: April 3, 2008Inventors: Yoshihisa Iwata, Katsuyuki Fujita, Yuui Shimizu
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Publication number: 20070258282Abstract: A magnetic memory device includes a magnetoresistance element which has first and second ends. First data is written into the magnetoresistance element by an electric current flowing from the first end to the second end. Second data is written into the magnetoresistance element by an electric current flowing from the second end to the first end. A first p-type MOSFET has one end connected to the first end. A second p-type MOSFET has one end connected to the second end. A first n-type MOSFET has one end connected to the first end. A second n-type MOSFET has one end connected to the second end. A current source circuit is connected to each another end of the first and second p-type MOSFETs and supplies an electric current. A current sink circuit is connected to each another end of the first and second n-type MOSFETs and draws an electric current.Type: ApplicationFiled: March 7, 2007Publication date: November 8, 2007Inventors: Yoshihiro UEDA, Tsuneo Inaba, Yuui Shimizu, Kiyotaro Itagaki