Abstract: A magnetic random access memory includes memory cells which store information using an internal magnetization direction. A first write line includes a first extending portion, a second extending portion and a first connection portion. The first extends portion extends along a first direction and has a first end and a second end. The second extending portion extends along the first direction and has a third end facing the first end and a fourth end facing the second end. The first connection portion connects the first end and the third end. A second write line and the first write line sandwiches one of the memory cells. First peripheral circuits are connected to the first connection portion and to at least one of the second end and the fourth end.

Abstract: A magnetic random access memory includes a memory cell array in which memory cells, each having a magnetoresistive element as a storage element, are arranged, word lines respectively connected to rows of the memory cell array, bit lines respectively connected to columns of the memory cell array, row decoders to select the word lines, and a column decoder to select the bit lines. To determine the value of storage data, electrical characteristic values based on storage data stored in the plurality of memory cells are detected, reference data is continuously written in the plurality of memory cells, the reference data written in the plurality of memory cells is continuously read out to detect electrical characteristic values based on the reference data, and the electrical characteristic values based on the storage data are compared with those based on the reference data.

Abstract: A magnetic random access memory includes memory cells which store information using an internal magnetization direction. A first write line includes a first extending portion, a second extending portion and a first connection portion. The first extends portion extends along a first direction and has a first end and a second end. The second extending portion extends along the first direction and has a third end facing the first end and a fourth end facing the second end. The first connection portion connects the first end and the third end. A second write line and the first write line sandwiches one of the memory cells. First peripheral circuits are connected to the first connection portion and to at least one of the second end and the fourth end.

Abstract: A semiconductor memory comprises a memory cell, a pair of reference cells for use in generation of a reference electric potential, a first read circuit which compares a read electric potential obtained from the memory cell with the reference electric potential and determines data in the memory cell, a second read circuit which detects a state of the pair of reference cells and outputs a detection signal indicating the state of the pair of reference cells, and a control circuit which controls a write operation for the pair of reference cells based on the detection signal.

Abstract: A semiconductor integrated circuit device includes a main memory cell array, redundant memory cell array, write current source, a common node connected to the write current source, a first selector connected between the common node and one-side ends of main write wirings and a second selector connected between the common node and one-side ends of redundant write wirings. The redundant memory cell array is arranged in a position apart from the main memory cell array and the write current source is commonly used by the main memory cell array and redundant memory cell array via the common node.

Abstract: A memory cell array is constructed by two-dimensionally arranging a plurality of memory cells each composed of a magnetoresistive element, in a row and column directions. Write word lines are provided along the row direction of the memory cell array. Write bit lines are provided along the column direction of the memory cell array. To write data, a pulse-like write current is applied to an appropriate word and bit lines to generate magnetic fields in the column and row directions. A combined magnetic field of the magnetic fields in the column and row directions is applied to a memory cell to write data. A control circuit controls the pulse width of the pulse-like write current applied to the word and bit lines so that the pulse width has a predetermined temperature dependence.

Abstract: A semiconductor memory device comprises word lines, bit lines, memory cells, a row decoder, a column decoder, and a write circuit. The word lines are formed along a first direction. The bit lines are formed along a second direction. Memory cells include magneto-resistive elements and are arranged at intersections of the word lines and the bit lines. The row decoder selects at least one of the word lines. The column decoder selects at least one of the bit lines. The write circuit supplies first and second write currents to a selected word line and selected bit line respectively and writes data into a selected memory cell arranged at the intersection of the selected word line and the selected bit line. The write circuit changes the current values of the first and second write currents according to a temperature change.

Abstract: A semiconductor memory comprises a memory cell, a pair of reference cells for use in generation of a reference electric potential, a first read circuit which compares a read electric potential obtained from the memory cell with the reference electric potential and determines data in the memory cell, a second read circuit which detects a state of the pair of reference cells and outputs a detection signal indicating the state of the pair of reference cells, and a control circuit which controls a write operation for the pair of reference cells based on the detection signal.

Abstract: A semiconductor memory device includes word lines, bit lines, first memory cells, second memory cells, a memory cell array, a row decoder, a row driver, a column decoder, a column driver, and a sense amplifier. The first memory cell includes a magneto-resistive element which has either a first resistance or a second resistance smaller than the first resistance. The second memory cell includes a magneto-resistive element which has a resistance between the first and second resistances. The memory cell array includes the first and second memory cells disposed in intersections of the word line and bit line. The row driver supplies a first write current to the word line. The column driver supplies a second write current to the bit line. The sense amplifier amplifies data read from the first memory cell.

Abstract: A magnetic random access memory includes a memory cell array in which memory cells, each having a magnetoresistive element as a storage element, are arranged, word lines respectively connected to rows of the memory cell array, bit lines respectively connected to columns of the memory cell array, row decoders to select the word lines, and a column decoder to select the bit lines. To determine the value of storage data, electrical characteristic values based on storage data stored in the plurality of memory cells are detected, reference data is continuously written in the plurality of memory cells, the reference data written in the plurality of memory cells is continuously read out to detect electrical characteristic values based on the reference data, and the electrical characteristic values based on the storage data are compared with those based on the reference data.

Abstract: A semiconductor integrated circuit device includes a main memory cell array, redundant memory cell array, write current source, a common node connected to the write current source, a first selector connected between the common node and one-side ends of main write wirings and a second selector connected between the common node and one-side ends of redundant write wirings. The redundant memory cell array is arranged in a position apart from the main memory cell array and the write current source is commonly used by the main memory cell array and redundant memory cell array via the common node.

Abstract: An MRAM has an internal test circuit. This test circuit detects a bit in a memory cell array, which has a shift in write characteristics, as a defective bit by using a method of applying a one-axis write current along an axis of hard magnetization.

Abstract: An MRAM has an internal test circuit. This test circuit detects a bit in a memory cell array, which has a shift in write characteristics, as a defective bit by using a method of applying a one-axis write current along an axis of hard magnetization.

Abstract: A semiconductor memory device comprises word lines, bit lines, memory cells, a row decoder, a column decoder, and a write circuit. The word lines are formed along a first direction. The bit lines are formed along a second direction. Memory cells include magneto-resistive elements and are arranged at intersections of the word lines and the bit lines. The row decoder selects at least one of the word lines. The column decoder selects at least one of the bit lines. The write circuit supplies first and second write currents to a selected word line and selected bit line respectively and writes data into a selected memory cell arranged at the intersection of the selected word line and the selected bit line. The write circuit changes the current values of the first and second write currents according to a temperature change.

Abstract: A memory cell array is constructed by two-dimensionally arranging a plurality of memory cells each composed of a magnetoresistive element, in a row and column directions. Write word lines are provided along the row direction of the memory cell array. Write bit lines are provided along the column direction of the memory cell array. To write data, a pulse-like write current is applied to an appropriate word and bit lines to generate magnetic fields in the column and row directions. A combined magnetic field of the magnetic fields in the column and row directions is applied to a memory cell to write data. A control circuit controls the pulse width of the pulse-like write current applied to the word and bit lines so that the pulse width has a predetermined temperature dependence.

Abstract: A semiconductor memory device includes word lines, bit lines, first memory cells, second memory cells, a memory cell array, a row decoder, a row driver, a column decoder, a column driver, and a sense amplifier. The first memory cell includes a magneto-resistive element which has either a first resistance or a second resistance smaller than the first resistance. The second memory cell includes a magneto-resistive element which has a resistance between the first and second resistances. The memory cell array includes the first and second memory cells disposed in intersections of the word line and bit line. The row driver supplies a first write current to the word line. The column driver supplies a second write current to the bit line. The sense amplifier amplifies data read from the first memory cell.