Patents by Inventor Yuuichi Kamimuta

Yuuichi Kamimuta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200227108
    Abstract: A semiconductor memory device according to one embodiment includes: a memory cell, the memory cell including a ferroelectric film; and a control circuit controlling the memory cell. Additionally, the control circuit determining whether the number of times of executions of a write process or an erase process on the memory cell has reached a predetermined number of times; and, if the number of times of executions has reached the predetermined number of times, executing a voltage application process in which a first voltage of a first polarity and a second voltage of a second polarity opposite to the first polarity are applied to the ferroelectric film.
    Type: Application
    Filed: March 26, 2020
    Publication date: July 16, 2020
    Applicant: Toshiba Memory Corporation
    Inventors: Yusuke Higashi, Yuuichi Kamimuta, Tsunehiro Ino
  • Patent number: 10636468
    Abstract: A semiconductor memory device according to one embodiment includes: a memory cell, the memory cell including a ferroelectric film; and a control circuit controlling the memory cell. Additionally, the control circuit determining whether the number of times of executions of a write process or an erase process on the memory cell has reached a predetermined number of times; and, if the number of times of executions has reached the predetermined number of times, executing a voltage application process in which a first voltage of a first polarity and a second voltage of a second polarity opposite to the first polarity are applied to the ferroelectric film.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: April 28, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yusuke Higashi, Yuuichi Kamimuta, Tsunehiro Ino
  • Publication number: 20200091160
    Abstract: A memory device according to an embodiment includes a first conductive layer, a second conductive layer, and a first layer provided between the first conductive layer and the second conductive layer and containing aluminum oxide that contains at least one first element selected from the group consisting of magnesium (Mg), silicon (Si), hafnium (Hf), tungsten (W), and ruthenium (Ru), and the aluminum oxide is a ferroelectric.
    Type: Application
    Filed: March 21, 2019
    Publication date: March 19, 2020
    Applicant: Toshiba Memory Corporation
    Inventors: Tsunehiro INO, Yuuichi KAMIMUTA
  • Publication number: 20200066868
    Abstract: A semiconductor memory device of an embodiment includes a semiconductor layer; a gate electrode including a first portion, a second portion provided to be spaced apart from the first portion, and a spacer provided between the first portion and the second portion; and a first insulating layer provided between the semiconductor layer and the gate electrode and including a first region containing a ferroelectric, a ferrielectric, or an anti-ferroelectric, a second region containing a ferroelectric, a ferrielectric, or an anti-ferroelectric, and a boundary region provided between the first region and the second region. The first region is positioned between the first portion and the semiconductor layer, the second region is positioned between the second portion and the semiconductor layer, the boundary region is positioned between the spacer and the semiconductor layer, and the boundary region has a chemical composition different from that of the spacer.
    Type: Application
    Filed: October 31, 2019
    Publication date: February 27, 2020
    Applicant: Toshiba Memory Corporation
    Inventors: Tsunehiro INO, Yusuke Higashi, Toshinori Numata, Yuuichi Kamimuta
  • Patent number: 10510862
    Abstract: A semiconductor memory device of an embodiment includes a semiconductor layer; a gate electrode including a first portion, a second portion provided to be spaced apart from the first portion, and a spacer provided between the first portion and the second portion; and a first insulating layer provided between the semiconductor layer and the gate electrode and including a first region containing a ferroelectric, a ferrielectric, or an anti-ferroelectric, a second region containing a ferroelectric, a ferrielectric, or an anti-ferroelectric, and a boundary region provided between the first region and the second region. The first region is positioned between the first portion and the semiconductor layer, the second region is positioned between the second portion and the semiconductor layer, the boundary region is positioned between the spacer and the semiconductor layer, and the boundary region has a chemical composition different from that of the spacer.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: December 17, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Tsunehiro Ino, Yusuke Higashi, Toshinori Numata, Yuuichi Kamimuta
  • Publication number: 20190319043
    Abstract: According to one embodiment, a semiconductor memory device includes a first conductive member, a first semiconductor member, and a first stacked member provided between the first conductive member and the first semiconductor member. The first stacked member includes a first insulating film, a second insulating film provided between the first insulating film and the first semiconductor member, first and second layers. The first layer includes aluminum and nitrogen and is provided between the first and second insulating films. A first thickness of the first layer along a first direction is 3 nm or less. The first direction is from the first semiconductor member toward the first conductive member. The second layer contacts the first layer, includes silicon and nitrogen, and is provided at one of a position between the first layer and the second insulating film or a position between the first layer and the first insulating film.
    Type: Application
    Filed: March 12, 2019
    Publication date: October 17, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Akira TAKASHIMA, Tsunehiro INO, Yuuichi KAMIMUTA, Ayaka SUKO
  • Patent number: 10446749
    Abstract: A memory device according to an embodiment includes a first conductive layer extending in a first direction, a second conductive layer extending in the first direction, a third conductive layer extending in a second direction intersecting the first direction, an insulating layer containing aluminum oxide provided between the first conductive layer and the second conductive layer, and a first insulating film including a first region located between the first conductive layer and the third conductive layer and a second region located between the insulating layer and the third conductive layer. The first region includes hafnium oxide mainly formed as an orthorhombic. The second region includes hafnium oxide mainly formed as crystals other than the orthorhombic.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: October 15, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Yoko Yoshimura, Hiromichi Kuriyama, Shoichi Kabuyanagi, Yuuichi Kamimuta, Chika Tanaka, Masumi Saitoh
  • Publication number: 20190296122
    Abstract: A semiconductor memory device of an embodiment includes a semiconductor layer; a gate electrode including a first portion, a second portion provided to be spaced apart from the first portion, and a spacer provided between the first portion and the second portion; and a first insulating layer provided between the semiconductor layer and the gate electrode and including a first region containing a ferroelectric, a ferrielectric, or an anti-ferroelectric, a second region containing a ferroelectric, a ferrielectric, or an anti-ferroelectric, and a boundary region provided between the first region and the second region. The first region is positioned between the first portion and the semiconductor layer, the second region is positioned between the second portion and the semiconductor layer, the boundary region is positioned between the spacer and the semiconductor layer, and the boundary region has a chemical composition different from that of the spacer.
    Type: Application
    Filed: September 18, 2018
    Publication date: September 26, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Tsunehiro INO, Yusuke Higashi, Toshinori Numata, Yuuichi Kamimuta
  • Publication number: 20190296234
    Abstract: A memory device according to an embodiment includes a first conductive layer extending in a first direction, a second conductive layer extending in the first direction, a third conductive layer extending in a second direction intersecting the first direction, an insulating layer containing aluminum oxide provided between the first conductive layer and the second conductive layer, and a first insulating film including a first region located between the first conductive layer and the third conductive layer and a second region located between the insulating layer and the third conductive layer. The first region includes hafnium oxide mainly formed as an orthorhombic. The second region includes hafnium oxide mainly formed as crystals other than the orthorhombic.
    Type: Application
    Filed: September 18, 2018
    Publication date: September 26, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Yoko Yoshimura, Hiromichi Kuriyama, Shoichi Kabuyanagi, Yuuichi Kamimuta, Chika Tanaka, Masumi Saitoh
  • Publication number: 20190287599
    Abstract: A semiconductor memory device according to one embodiment includes: a memory cell, the memory cell including a ferroelectric film; and a control circuit controlling the memory cell. Additionally, the control circuit determining whether the number of times of executions of a write process or an erase process on the memory cell has reached a predetermined number of times; and, if the number of times of executions has reached the predetermined number of times, executing a voltage application process in which a first voltage of a first polarity and a second voltage of a second polarity opposite to the first polarity are applied to the ferroelectric film.
    Type: Application
    Filed: August 27, 2018
    Publication date: September 19, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Yusuke Higashi, Yuuichi Kamimuta, Tsunehiro Ino
  • Patent number: 10249818
    Abstract: According to one embodiment, a memory element includes a first layer, a second layer, and a third layer. The first layer is conductive. The second layer is conductive. The third layer includes hafnium oxide and is provided between the first layer and the second layer. The first layer includes a first region, a second region, and a third region. The first region includes a first element and a first metallic element. The first element is selected from a group consisting of carbon and nitrogen. The second region includes a second metallic element and is provided between the first region and the third layer. The third region includes titanium oxide and is provided between the second region and the third layer.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: April 2, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Marina Yamaguchi, Shosuke Fujii, Riichiro Takaishi, Yuuichi Kamimuta, Shoichi Kabuyanagi, Masumi Saitoh
  • Publication number: 20190088664
    Abstract: A memory device according to an embodiment includes a first conductive layer; a second conductive layer; a ferroelectric layer provided between the first conductive layer and the second conductive layer and containing hafnium oxide; a paraelectric layer provided between the first conductive layer and the ferroelectric layer and containing a first oxide; and an oxide layer provided between the paraelectric layer and the ferroelectric layer and containing a second oxide having an oxygen area density lower than an oxygen area density of the first oxide.
    Type: Application
    Filed: February 26, 2018
    Publication date: March 21, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Shoichi KABUYANAGI, Yuuichi Kamimuta, Masumi Saitoh, Marina Yamaguchi
  • Publication number: 20190088870
    Abstract: According to one embodiment, a memory element includes a first layer, a second layer, and a third layer. The first layer is conductive. The second layer is conductive. The third layer includes hafnium oxide and is provided between the first layer and the second layer. The first layer includes a first region, a second region, and a third region. The first region includes a first element and a first metallic element. The first element is selected from a group consisting of carbon and nitrogen. The second region includes a second metallic element and is provided between the first region and the third layer. The third region includes titanium oxide and is provided between the second region and the third layer.
    Type: Application
    Filed: March 6, 2018
    Publication date: March 21, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Marina YAMAGUCHI, Shosuke Fujii, Riichiro Takaishi, Yuuichi Kamimuta, Shoichi Kabuyanagi, Masumi Saitoh
  • Patent number: 9997569
    Abstract: According to one embodiment, a memory device includes a first electrode, a second electrode, a first layer, and a second layer. The first electrode includes a first element. The first layer is provided between the first electrode and the second electrode. The first layer includes at least one of an insulator or a first semiconductor. The second layer is provided between the first layer and the second electrode. The second layer includes a first region and a second region. The second region is provided between the first region and the second electrode. The second region includes a second element. A standard electrode potential of the second element is lower than a standard electrode potential of the first element. A concentration of nitrogen in the first region is higher than a concentration of nitrogen in the second region.
    Type: Grant
    Filed: August 3, 2016
    Date of Patent: June 12, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Marina Yamaguchi, Shosuke Fujii, Yuuichi Kamimuta, Takayuki Ishikawa, Masumi Saitoh
  • Patent number: 9761798
    Abstract: A storage device of an embodiment includes a first conductive layer containing a first element selected from the group consisting of Si, Ge, and a metal element, a second conductive layer including a first region containing a first metal element and carbon or nitrogen, a second region containing a second metal element and carbon or nitrogen, and a third region provided between the first region and the second region, the third region containing a third metal element, the standard free energy of formation of an oxide of the third metal element being smaller than the standard free energy of formation of an oxide of the first element, a ferroelectric layer provided between the first conductive layer and the second conductive layer, and a paraelectric layer provided between the first conductive layer and the ferroelectric layer.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: September 12, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yuuichi Kamimuta, Shosuke Fujii, Masumi Saitoh
  • Patent number: 9721951
    Abstract: According to one embodiment, a semiconductor device includes a first complementary semiconductor device provided on a semiconductor substrate, and including a CMOS circuit, a metal electrode provided above the first complementary semiconductor device, a semiconductor layer provided above the metal electrode, including an nMOS region and a pMOS region separated from each other, and containing Ge; and a second complementary semiconductor device including an nMOSFET provided on the first portion of the semiconductor layer and a pMOSFET provided on the second portion of the semiconductor layer.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: August 1, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Keiji Ikeda, Tsutomu Tezuka, Yuuichi Kamimuta, Kiyoe Furuse
  • Publication number: 20170040380
    Abstract: According to one embodiment, a memory device includes a first electrode, a second electrode, a first layer, and a second layer. The first electrode includes a first element. The first layer is provided between the first electrode and the second electrode. The first layer includes at least one of an insulator or a first semiconductor. The second layer is provided between the first layer and the second electrode. The second layer includes a first region and a second region. The second region is provided between the first region and the second electrode. The second region includes a second element. A standard electrode potential of the second element is lower than a standard electrode potential of the first element. A concentration of nitrogen in the first region is higher than a concentration of nitrogen in the second region.
    Type: Application
    Filed: August 3, 2016
    Publication date: February 9, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Marina YAMAGUCHI, Shosuke FUJII, Yuuichi KAMIMUTA, Takayuki ISHIKAWA, Masumi SAITOH
  • Patent number: 9543376
    Abstract: According to one embodiment, a semiconductor device includes a semiconductor layer including Ge; and a metal Ge compound region provided in a surface portion of the semiconductor layer. Sn is included in an interface portion between the semiconductor layer and the metal Ge compound region. A lattice plane of the semiconductor layer matches with a lattice plane of the metal Ge compound region.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: January 10, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masahiro Koike, Yuuichi Kamimuta, Tsutomu Tezuka
  • Publication number: 20160359109
    Abstract: A storage device of an embodiment includes a first conductive layer containing a first element selected from the group consisting of Si, Ge, and a metal element, a second conductive layer including a first region containing a first metal element and carbon or nitrogen, a second region containing a second metal element and carbon or nitrogen, and a third region provided between the first region and the second region, the third region containing a third metal element, the standard free energy of formation of an oxide of the third metal element being smaller than the standard free energy of formation of an oxide of the first element, a ferroelectric layer provided between the first conductive layer and the second conductive layer, and a paraelectric layer provided between the first conductive layer and the ferroelectric layer.
    Type: Application
    Filed: March 7, 2016
    Publication date: December 8, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yuuichi KAMIMUTA, Shosuke FUJII, Masumi SAITOH
  • Publication number: 20160071921
    Abstract: According to one embodiment, a semiconductor device includes a semiconductor layer including Ge; and a metal Ge compound region provided in a surface portion of the semiconductor layer. Sn is included in an interface portion between the semiconductor layer and the metal Ge compound region. A lattice plane of the semiconductor layer matches with a lattice plane of the metal Ge compound region.
    Type: Application
    Filed: October 30, 2015
    Publication date: March 10, 2016
    Inventors: Masahiro KOIKE, Yuuichi KAMIMUTA, Tsutomu TEZUKA