Patents by Inventor Yuuichi Kamimuta
Yuuichi Kamimuta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200091160Abstract: A memory device according to an embodiment includes a first conductive layer, a second conductive layer, and a first layer provided between the first conductive layer and the second conductive layer and containing aluminum oxide that contains at least one first element selected from the group consisting of magnesium (Mg), silicon (Si), hafnium (Hf), tungsten (W), and ruthenium (Ru), and the aluminum oxide is a ferroelectric.Type: ApplicationFiled: March 21, 2019Publication date: March 19, 2020Applicant: Toshiba Memory CorporationInventors: Tsunehiro INO, Yuuichi KAMIMUTA
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Publication number: 20200066868Abstract: A semiconductor memory device of an embodiment includes a semiconductor layer; a gate electrode including a first portion, a second portion provided to be spaced apart from the first portion, and a spacer provided between the first portion and the second portion; and a first insulating layer provided between the semiconductor layer and the gate electrode and including a first region containing a ferroelectric, a ferrielectric, or an anti-ferroelectric, a second region containing a ferroelectric, a ferrielectric, or an anti-ferroelectric, and a boundary region provided between the first region and the second region. The first region is positioned between the first portion and the semiconductor layer, the second region is positioned between the second portion and the semiconductor layer, the boundary region is positioned between the spacer and the semiconductor layer, and the boundary region has a chemical composition different from that of the spacer.Type: ApplicationFiled: October 31, 2019Publication date: February 27, 2020Applicant: Toshiba Memory CorporationInventors: Tsunehiro INO, Yusuke Higashi, Toshinori Numata, Yuuichi Kamimuta
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Patent number: 10510862Abstract: A semiconductor memory device of an embodiment includes a semiconductor layer; a gate electrode including a first portion, a second portion provided to be spaced apart from the first portion, and a spacer provided between the first portion and the second portion; and a first insulating layer provided between the semiconductor layer and the gate electrode and including a first region containing a ferroelectric, a ferrielectric, or an anti-ferroelectric, a second region containing a ferroelectric, a ferrielectric, or an anti-ferroelectric, and a boundary region provided between the first region and the second region. The first region is positioned between the first portion and the semiconductor layer, the second region is positioned between the second portion and the semiconductor layer, the boundary region is positioned between the spacer and the semiconductor layer, and the boundary region has a chemical composition different from that of the spacer.Type: GrantFiled: September 18, 2018Date of Patent: December 17, 2019Assignee: Toshiba Memory CorporationInventors: Tsunehiro Ino, Yusuke Higashi, Toshinori Numata, Yuuichi Kamimuta
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Publication number: 20190319043Abstract: According to one embodiment, a semiconductor memory device includes a first conductive member, a first semiconductor member, and a first stacked member provided between the first conductive member and the first semiconductor member. The first stacked member includes a first insulating film, a second insulating film provided between the first insulating film and the first semiconductor member, first and second layers. The first layer includes aluminum and nitrogen and is provided between the first and second insulating films. A first thickness of the first layer along a first direction is 3 nm or less. The first direction is from the first semiconductor member toward the first conductive member. The second layer contacts the first layer, includes silicon and nitrogen, and is provided at one of a position between the first layer and the second insulating film or a position between the first layer and the first insulating film.Type: ApplicationFiled: March 12, 2019Publication date: October 17, 2019Applicant: TOSHIBA MEMORY CORPORATIONInventors: Akira TAKASHIMA, Tsunehiro INO, Yuuichi KAMIMUTA, Ayaka SUKO
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Patent number: 10446749Abstract: A memory device according to an embodiment includes a first conductive layer extending in a first direction, a second conductive layer extending in the first direction, a third conductive layer extending in a second direction intersecting the first direction, an insulating layer containing aluminum oxide provided between the first conductive layer and the second conductive layer, and a first insulating film including a first region located between the first conductive layer and the third conductive layer and a second region located between the insulating layer and the third conductive layer. The first region includes hafnium oxide mainly formed as an orthorhombic. The second region includes hafnium oxide mainly formed as crystals other than the orthorhombic.Type: GrantFiled: September 18, 2018Date of Patent: October 15, 2019Assignee: Toshiba Memory CorporationInventors: Yoko Yoshimura, Hiromichi Kuriyama, Shoichi Kabuyanagi, Yuuichi Kamimuta, Chika Tanaka, Masumi Saitoh
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Publication number: 20190296234Abstract: A memory device according to an embodiment includes a first conductive layer extending in a first direction, a second conductive layer extending in the first direction, a third conductive layer extending in a second direction intersecting the first direction, an insulating layer containing aluminum oxide provided between the first conductive layer and the second conductive layer, and a first insulating film including a first region located between the first conductive layer and the third conductive layer and a second region located between the insulating layer and the third conductive layer. The first region includes hafnium oxide mainly formed as an orthorhombic. The second region includes hafnium oxide mainly formed as crystals other than the orthorhombic.Type: ApplicationFiled: September 18, 2018Publication date: September 26, 2019Applicant: Toshiba Memory CorporationInventors: Yoko Yoshimura, Hiromichi Kuriyama, Shoichi Kabuyanagi, Yuuichi Kamimuta, Chika Tanaka, Masumi Saitoh
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Publication number: 20190296122Abstract: A semiconductor memory device of an embodiment includes a semiconductor layer; a gate electrode including a first portion, a second portion provided to be spaced apart from the first portion, and a spacer provided between the first portion and the second portion; and a first insulating layer provided between the semiconductor layer and the gate electrode and including a first region containing a ferroelectric, a ferrielectric, or an anti-ferroelectric, a second region containing a ferroelectric, a ferrielectric, or an anti-ferroelectric, and a boundary region provided between the first region and the second region. The first region is positioned between the first portion and the semiconductor layer, the second region is positioned between the second portion and the semiconductor layer, the boundary region is positioned between the spacer and the semiconductor layer, and the boundary region has a chemical composition different from that of the spacer.Type: ApplicationFiled: September 18, 2018Publication date: September 26, 2019Applicant: Toshiba Memory CorporationInventors: Tsunehiro INO, Yusuke Higashi, Toshinori Numata, Yuuichi Kamimuta
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Publication number: 20190287599Abstract: A semiconductor memory device according to one embodiment includes: a memory cell, the memory cell including a ferroelectric film; and a control circuit controlling the memory cell. Additionally, the control circuit determining whether the number of times of executions of a write process or an erase process on the memory cell has reached a predetermined number of times; and, if the number of times of executions has reached the predetermined number of times, executing a voltage application process in which a first voltage of a first polarity and a second voltage of a second polarity opposite to the first polarity are applied to the ferroelectric film.Type: ApplicationFiled: August 27, 2018Publication date: September 19, 2019Applicant: TOSHIBA MEMORY CORPORATIONInventors: Yusuke Higashi, Yuuichi Kamimuta, Tsunehiro Ino
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Patent number: 10249818Abstract: According to one embodiment, a memory element includes a first layer, a second layer, and a third layer. The first layer is conductive. The second layer is conductive. The third layer includes hafnium oxide and is provided between the first layer and the second layer. The first layer includes a first region, a second region, and a third region. The first region includes a first element and a first metallic element. The first element is selected from a group consisting of carbon and nitrogen. The second region includes a second metallic element and is provided between the first region and the third layer. The third region includes titanium oxide and is provided between the second region and the third layer.Type: GrantFiled: March 6, 2018Date of Patent: April 2, 2019Assignee: Toshiba Memory CorporationInventors: Marina Yamaguchi, Shosuke Fujii, Riichiro Takaishi, Yuuichi Kamimuta, Shoichi Kabuyanagi, Masumi Saitoh
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Publication number: 20190088664Abstract: A memory device according to an embodiment includes a first conductive layer; a second conductive layer; a ferroelectric layer provided between the first conductive layer and the second conductive layer and containing hafnium oxide; a paraelectric layer provided between the first conductive layer and the ferroelectric layer and containing a first oxide; and an oxide layer provided between the paraelectric layer and the ferroelectric layer and containing a second oxide having an oxygen area density lower than an oxygen area density of the first oxide.Type: ApplicationFiled: February 26, 2018Publication date: March 21, 2019Applicant: Toshiba Memory CorporationInventors: Shoichi KABUYANAGI, Yuuichi Kamimuta, Masumi Saitoh, Marina Yamaguchi
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Publication number: 20190088870Abstract: According to one embodiment, a memory element includes a first layer, a second layer, and a third layer. The first layer is conductive. The second layer is conductive. The third layer includes hafnium oxide and is provided between the first layer and the second layer. The first layer includes a first region, a second region, and a third region. The first region includes a first element and a first metallic element. The first element is selected from a group consisting of carbon and nitrogen. The second region includes a second metallic element and is provided between the first region and the third layer. The third region includes titanium oxide and is provided between the second region and the third layer.Type: ApplicationFiled: March 6, 2018Publication date: March 21, 2019Applicant: Toshiba Memory CorporationInventors: Marina YAMAGUCHI, Shosuke Fujii, Riichiro Takaishi, Yuuichi Kamimuta, Shoichi Kabuyanagi, Masumi Saitoh
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Patent number: 9997569Abstract: According to one embodiment, a memory device includes a first electrode, a second electrode, a first layer, and a second layer. The first electrode includes a first element. The first layer is provided between the first electrode and the second electrode. The first layer includes at least one of an insulator or a first semiconductor. The second layer is provided between the first layer and the second electrode. The second layer includes a first region and a second region. The second region is provided between the first region and the second electrode. The second region includes a second element. A standard electrode potential of the second element is lower than a standard electrode potential of the first element. A concentration of nitrogen in the first region is higher than a concentration of nitrogen in the second region.Type: GrantFiled: August 3, 2016Date of Patent: June 12, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Marina Yamaguchi, Shosuke Fujii, Yuuichi Kamimuta, Takayuki Ishikawa, Masumi Saitoh
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Patent number: 9761798Abstract: A storage device of an embodiment includes a first conductive layer containing a first element selected from the group consisting of Si, Ge, and a metal element, a second conductive layer including a first region containing a first metal element and carbon or nitrogen, a second region containing a second metal element and carbon or nitrogen, and a third region provided between the first region and the second region, the third region containing a third metal element, the standard free energy of formation of an oxide of the third metal element being smaller than the standard free energy of formation of an oxide of the first element, a ferroelectric layer provided between the first conductive layer and the second conductive layer, and a paraelectric layer provided between the first conductive layer and the ferroelectric layer.Type: GrantFiled: March 7, 2016Date of Patent: September 12, 2017Assignee: TOSHIBA MEMORY CORPORATIONInventors: Yuuichi Kamimuta, Shosuke Fujii, Masumi Saitoh
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Patent number: 9721951Abstract: According to one embodiment, a semiconductor device includes a first complementary semiconductor device provided on a semiconductor substrate, and including a CMOS circuit, a metal electrode provided above the first complementary semiconductor device, a semiconductor layer provided above the metal electrode, including an nMOS region and a pMOS region separated from each other, and containing Ge; and a second complementary semiconductor device including an nMOSFET provided on the first portion of the semiconductor layer and a pMOSFET provided on the second portion of the semiconductor layer.Type: GrantFiled: December 19, 2014Date of Patent: August 1, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Keiji Ikeda, Tsutomu Tezuka, Yuuichi Kamimuta, Kiyoe Furuse
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Publication number: 20170040380Abstract: According to one embodiment, a memory device includes a first electrode, a second electrode, a first layer, and a second layer. The first electrode includes a first element. The first layer is provided between the first electrode and the second electrode. The first layer includes at least one of an insulator or a first semiconductor. The second layer is provided between the first layer and the second electrode. The second layer includes a first region and a second region. The second region is provided between the first region and the second electrode. The second region includes a second element. A standard electrode potential of the second element is lower than a standard electrode potential of the first element. A concentration of nitrogen in the first region is higher than a concentration of nitrogen in the second region.Type: ApplicationFiled: August 3, 2016Publication date: February 9, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Marina YAMAGUCHI, Shosuke FUJII, Yuuichi KAMIMUTA, Takayuki ISHIKAWA, Masumi SAITOH
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Patent number: 9543376Abstract: According to one embodiment, a semiconductor device includes a semiconductor layer including Ge; and a metal Ge compound region provided in a surface portion of the semiconductor layer. Sn is included in an interface portion between the semiconductor layer and the metal Ge compound region. A lattice plane of the semiconductor layer matches with a lattice plane of the metal Ge compound region.Type: GrantFiled: October 30, 2015Date of Patent: January 10, 2017Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Masahiro Koike, Yuuichi Kamimuta, Tsutomu Tezuka
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Publication number: 20160359109Abstract: A storage device of an embodiment includes a first conductive layer containing a first element selected from the group consisting of Si, Ge, and a metal element, a second conductive layer including a first region containing a first metal element and carbon or nitrogen, a second region containing a second metal element and carbon or nitrogen, and a third region provided between the first region and the second region, the third region containing a third metal element, the standard free energy of formation of an oxide of the third metal element being smaller than the standard free energy of formation of an oxide of the first element, a ferroelectric layer provided between the first conductive layer and the second conductive layer, and a paraelectric layer provided between the first conductive layer and the ferroelectric layer.Type: ApplicationFiled: March 7, 2016Publication date: December 8, 2016Applicant: Kabushiki Kaisha ToshibaInventors: Yuuichi KAMIMUTA, Shosuke FUJII, Masumi SAITOH
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Publication number: 20160071921Abstract: According to one embodiment, a semiconductor device includes a semiconductor layer including Ge; and a metal Ge compound region provided in a surface portion of the semiconductor layer. Sn is included in an interface portion between the semiconductor layer and the metal Ge compound region. A lattice plane of the semiconductor layer matches with a lattice plane of the metal Ge compound region.Type: ApplicationFiled: October 30, 2015Publication date: March 10, 2016Inventors: Masahiro KOIKE, Yuuichi KAMIMUTA, Tsutomu TEZUKA
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Publication number: 20150102419Abstract: According to one embodiment, a semiconductor device includes a first complementary semiconductor device provided on a semiconductor substrate, and including a CMOS circuit, a metal electrode provided above the first complementary semiconductor device, a semiconductor layer provided above the metal electrode, including an nMOS region and a pMOS region separated from each other, and containing Ge; and a second complementary semiconductor device including an nMOSFET provided on the first portion of the semiconductor layer and a pMOSFET provided on the second portion of the semiconductor layer.Type: ApplicationFiled: December 19, 2014Publication date: April 16, 2015Inventors: Keiji IKEDA, Tsutomu TEZUKA, Yuuichi KAMIMUTA, Kiyoe FURUSE
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Publication number: 20150008492Abstract: According to one embodiment, a semiconductor device of a junctionless structure includes a semiconductor layer of a first conductivity type. A pair of source/drain electrodes at a distance is on the semiconductor layer. A gate insulating film is on the semiconductor layer between the source/drain electrodes. A gate electrode is on the gate insulating film. The semiconductor layer has two or more kinds of impurities. One kind of the two or more kinds of impurities is an element selected from a group of chalcogens, and another kind of the two or more kinds of impurities is a first conductivity type impurity.Type: ApplicationFiled: September 26, 2014Publication date: January 8, 2015Inventors: Masahiro Koike, Yuuichi Kamimuta, Tsutomu Tezuka