Patents by Inventor Yuusuke Takano

Yuusuke Takano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220216184
    Abstract: A semiconductor device includes a first semiconductor chip having a first surface and a second surface; a first adhesive layer on the first surface; a second semiconductor chip that includes a third surface and a fourth surface, and a connection bump on the third surface. The connection bump is coupled to the first adhesive layer. The semiconductor device includes a wiring substrate connected to the connection bump. The semiconductor device includes a first resin layer covering the connection bump between the second semiconductor chip and the wiring substrate, and covers one side surface of the second semiconductor chip connecting the third surface and the fourth surface. The first adhesive layer covers an upper portion of the at least one side surface. The first resin layer covers a lower portion of the t least one side surface. The first adhesive layer and the first resin layer contact each other.
    Type: Application
    Filed: March 22, 2022
    Publication date: July 7, 2022
    Applicant: Kioxia Corporation
    Inventors: Takeori MAEDA, Yuusuke TAKANO, Soichi HOMMA
  • Patent number: 11302675
    Abstract: A semiconductor device includes a first semiconductor chip having a first surface and a second surface; a first adhesive layer on the first surface; a second semiconductor chip that includes a third surface and a fourth surface, and a connection bump on the third surface. The connection bump is coupled to the first adhesive layer. The semiconductor device includes a wiring substrate connected to the connection bump. The semiconductor device includes a first resin layer covering the connection bump between the second semiconductor chip and the wiring substrate, and covers one side surface of the second semiconductor chip connecting the third surface and the fourth surface. The first adhesive layer covers an upper portion of the at least one side surface. The first resin layer covers a lower portion of the at least one side surface. The first adhesive layer and the first resin layer contact each other.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: April 12, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Takeori Maeda, Yuusuke Takano, Soichi Homma
  • Publication number: 20210257336
    Abstract: A semiconductor device includes a first semiconductor chip having a first surface and a second surface; a first adhesive layer on the first surface; a second semiconductor chip that includes a third surface and a fourth surface, and a connection bump on the third surface. The connection bump is coupled to the first adhesive layer. The semiconductor device includes a wiring substrate connected to the connection bump. The semiconductor device includes a first resin layer covering the connection bump between the second semiconductor chip and the wiring substrate, and covers one side surface of the second semiconductor chip connecting the third surface and the fourth surface. The first adhesive layer covers an upper portion of the at least one side surface. The first resin layer covers a lower portion of the at least one side surface. The first adhesive layer and the first resin layer contact each other.
    Type: Application
    Filed: August 31, 2020
    Publication date: August 19, 2021
    Applicant: Kioxia Corporation
    Inventors: Takeori MAEDA, Yuusuke TAKANO, Soichi HOMMA
  • Patent number: 10546818
    Abstract: A semiconductor package includes a substrate, a semiconductor element disposed on the substrate, an encapsulating layer covering side surfaces and a top surface of the semiconductor element, an electromagnetic shield layer covering side surfaces of the substrate and side surfaces and a top surface of the encapsulating layer, and a titanium oxide layer formed above a top surface of the electromagnetic shield layer, and including a first portion containing divalent titanium oxide and a second portion containing tetravalent titanium oxide.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: January 28, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Yuusuke Takano
  • Publication number: 20190244912
    Abstract: According to one embodiment, a semiconductor device includes a wiring board that has a first surface and a second surface opposed to the first surface, a semiconductor chip provided on the first surface, external connection terminals provided on the second surface, a sealing resin layer provided on the first surface, and a conductive shield layer that covers at least a portion of a side surface of the wiring board and the sealing resin layer. The wiring board includes a first ground wire that is electrically connected to the conductive shield layer, and a second ground wire that is electrically connected to the conductive shield layer and is electrically insulated from the first ground wire.
    Type: Application
    Filed: April 17, 2019
    Publication date: August 8, 2019
    Inventors: Yuusuke TAKANO, Yoshiaki GOTO, Takeshi WATANABE, Takashi IMOTO
  • Patent number: 10312197
    Abstract: According to one embodiment, a method of manufacturing a semiconductor device includes forming a sealing resin layer containing an inorganic filler so as to seal a semiconductor chip, removing a portion of the surface of the sealing resin layer by dry etching such that a portion of the inorganic filler is exposed, and forming a shield layer so as to cover at least the sealing resin layer.
    Type: Grant
    Filed: September 2, 2014
    Date of Patent: June 4, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Yuusuke Takano, Takashi Imoto, Takeshi Watanabe, Soichi Homma, Katsunori Shibuya
  • Patent number: 10115674
    Abstract: According to one embodiment, in a method for manufacturing a semiconductor device, a semiconductor chip is provided on a first surface of a substrate having the first surface, a second surface opposite to the first surface, and a side surface between the first surface and the second surface. A resin that seals the first surface of the semiconductor chip is formed on the semiconductor chip. A conductive film electrically connectable to a ground potential source is formed on an upper surface of the resin and a side surface of the resin. A metal oxide film or a metal nitride film is formed on the conductive film by depositing metal on the conductive film in an environment containing oxygen or nitrogen.
    Type: Grant
    Filed: August 10, 2016
    Date of Patent: October 30, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yuusuke Takano, Takeshi Watanabe
  • Publication number: 20180277488
    Abstract: A semiconductor package includes a substrate, a semiconductor element disposed on the substrate, an encapsulating layer covering side surfaces and a top surface of the semiconductor element, an electromagnetic shield layer covering side surfaces of the substrate and side surfaces and a top surface of the encapsulating layer, and a titanium oxide layer formed above a top surface of the electromagnetic shield layer, and including a first portion containing divalent titanium oxide and a second portion containing tetravalent titanium oxide.
    Type: Application
    Filed: August 31, 2017
    Publication date: September 27, 2018
    Inventor: Yuusuke TAKANO
  • Patent number: 9881876
    Abstract: A semiconductor device includes a wiring substrate that includes a base having a first surface, a second surface, and a wiring, a semiconductor chip located on the first surface, an external connection terminal located on the second surface and electrically connected to the wiring, a sealing resin layer covering the semiconductor chip, a metal compound layer containing a metal nitride in contact with a surface of the sealing resin layer, and a conductive shield layer covering the sealing resin layer with the metal compound layer interposed between the conductive shield layer and the sealing resin layer. The wiring is exposed at a side surface of the wiring substrate, and is electrically connected to the conductive shield layer.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: January 30, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Soichi Homma, Yuusuke Takano
  • Patent number: 9824905
    Abstract: A semiconductor manufacturing device has an upper cover configured to be arranged above top surface of unshielded semiconductor device which are mounted on a tray placed on a carrier to go through electromagnetic shielding, and a displacement detector configured to detect an abnormality when the upper cover is raised by at least one of the semiconductor device which is brought into contact with a bottom surface of the upper cover.
    Type: Grant
    Filed: September 10, 2014
    Date of Patent: November 21, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Katsunori Shibuya, Takashi Imoto, Soichi Homma, Takeshi Watanabe, Yuusuke Takano
  • Patent number: 9646908
    Abstract: In a method for manufacturing a semiconductor device, a resin layer including an inorganic filler is molded on a surface of a substrate which includes semiconductor elements attached thereto by an adhesive, and terminals electrically connected to the semiconductor elements on another surface thereof. The molded substrate is cut so as to expose a conductive body electrically connected to an external terminal maintainable at ground potential. The surface of the resin layer of the substrate is sputter-etched in a vacuum environment, in a state where a plurality of the cut substrates is provided in a tray so that the surface of the substrate faces the tray. A metal layer is sputtered so as to be electrically connected to the conductive body on the surface and the cut surface in a state where the substrate is provided in the tray while maintaining the vacuum environment after sputter-etching.
    Type: Grant
    Filed: July 22, 2016
    Date of Patent: May 9, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Soichi Homma, Masaya Shima, Yuusuke Takano, Takeshi Watanabe, Katsunori Shibuya
  • Publication number: 20170077040
    Abstract: According to one embodiment, in a method for manufacturing a semiconductor device, a semiconductor chip is provided on a first surface of a substrate having the first surface, a second surface opposite to the first surface, and a side surface between the first surface and the second surface. A resin that seals the first surface of the semiconductor chip is formed on the semiconductor chip. A conductive film electrically connectable to a ground potential source is formed on an upper surface of the resin and a side surface of the resin. A metal oxide film or a metal nitride film is formed on the conductive film by depositing metal on the conductive film in an environment containing oxygen or nitrogen.
    Type: Application
    Filed: August 10, 2016
    Publication date: March 16, 2017
    Inventors: Yuusuke TAKANO, Takeshi WATANABE
  • Publication number: 20170033086
    Abstract: A semiconductor device includes a wiring substrate that includes a base having a first surface, a second surface, and a wiring, a semiconductor chip located on the first surface, an external connection terminal located on the second surface and electrically connected to the wiring, a sealing resin layer covering the semiconductor chip, a metal compound layer containing a metal nitride in contact with a surface of the sealing resin layer, and a conductive shield layer covering the sealing resin layer with the metal compound layer interposed between the conductive shield layer and the sealing resin layer. The wiring is exposed at a side surface of the wiring substrate, and is electrically connected to the conductive shield layer.
    Type: Application
    Filed: July 29, 2016
    Publication date: February 2, 2017
    Inventors: Soichi HOMMA, Yuusuke TAKANO
  • Publication number: 20170025321
    Abstract: In a method for manufacturing a semiconductor device, a resin layer including an inorganic filler is molded on a surface of a substrate which includes semiconductor elements attached thereto by an adhesive, and terminals electrically connected to the semiconductor elements on another surface thereof. The molded substrate is cut so as to expose a conductive body electrically connected to an external terminal maintainable at ground potential. The surface of the resin layer of the substrate is sputter-etched in a vacuum environment, in a state where a plurality of the cut substrates is provided in a tray so that the surface of the substrate faces the tray. A metal layer is sputtered so as to be electrically connected to the conductive body on the surface and the cut surface in a state where the substrate is provided in the tray while maintaining the vacuum environment after sputter-etching.
    Type: Application
    Filed: July 22, 2016
    Publication date: January 26, 2017
    Inventors: Soichi HOMMA, Masaya SHIMA, Yuusuke TAKANO, Takeshi WATANABE, Katsunori SHIBUYA
  • Patent number: 9458535
    Abstract: A semiconductor manufacturing device has a conveyor configured to convey a tray having an unshielded semiconductor device mounted thereon to go through electromagnetic shielding, and a controller configured to control the conveyor. The controller performs control to take out the tray from a tray supply storage storing trays each having an unshielded semiconductor device mounted thereon to go through the electromagnetic shielding, place the tray on a carrier, and convey this carrier to a sputtering device which coats the unshielded semiconductor device with a sputtering material for the electromagnetic shielding, and the controller performs control to take out, from the sputtering device, the carrier having the tray placed thereon with an electromagnetically shielded semiconductor device being mounted on the tray, convey the tray, pick up the tray having the electromagnetically shielded semiconductor device mounted thereon from the carrier, and store the tray in the tray supply storage.
    Type: Grant
    Filed: September 10, 2014
    Date of Patent: October 4, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Katsunori Shibuya, Takashi Imoto, Soichi Homma, Takeshi Watanabe, Yuusuke Takano
  • Patent number: 9385090
    Abstract: A semiconductor device includes a conductive shield layer that has a first portion covering a surface of a sealing resin layer and a second portion covering side surfaces of the sealing resin layer and side surfaces of the substrate. Portions of wiring layers, including a grounding wire, on or in the substrate have cut planes which are exposed to the side surfaces of the substrate and spread out in a thickness direction of the substrate. A cut plane of the grounding wire is electrically connected to the shield layer. An area of the cut plane of the grounding wire is larger than an area of a cross section of the grounding wire parallel to, and inward of the substrate from, the cut plane of the grounding wire.
    Type: Grant
    Filed: September 2, 2014
    Date of Patent: July 5, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Katsunori Shibuya, Takashi Imoto, Soichi Homma, Takeshi Watanabe, Yuusuke Takano
  • Patent number: 9349694
    Abstract: According to one embodiment, a semiconductor device includes a substrate. A semiconductor chip is disposed on a first surface of the substrate. The semiconductor chip is covered with a sealing material. A front surface and a side surface of the sealing material are covered with a conductive film. On an outer edge of a substrate-side of the semiconductor device, a step or a trench is formed.
    Type: Grant
    Filed: August 29, 2014
    Date of Patent: May 24, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsunori Shibuya, Soichi Homma, Yuusuke Takano, Shinpei Ishida
  • Patent number: 9209053
    Abstract: In a manufacturing method of a semiconductor device according to an embodiment, a plurality of semiconductor packages each including a semiconductor chip mounted on a wiring board and a sealing resin layer as objects to be processed, and a tray including a plurality of housing parts are prepared. A depressed portion having a non-penetrating shape or a penetrating shape is formed in the housing part. The semiconductor packages are disposed in the plural housing parts respectively. By sputtering a metal material on the semiconductor package housed in the tray, a conductive shield layer is formed.
    Type: Grant
    Filed: September 10, 2014
    Date of Patent: December 8, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yoshiaki Goto, Takashi Imoto, Takeshi Watanabe, Yuusuke Takano, Yusuke Akada, Yuji Karakane, Yoshinori Okayama, Akihiko Yanagida
  • Publication number: 20150170988
    Abstract: According to one embodiment, a plurality of semiconductor devices is mounted on a wiring substrate. A surface, on which a semiconductor devices of the wiring substrate are mounted, and the plurality of semiconductor devices are sealed by using a sealing resin. The wiring substrate which is sealed is cut and thus separated into semiconductor apparatuses. The semiconductor apparatuses after the separation are heated. A shield layer is formed by metal sputtering over wiring exposed at the edge of the cut wiring substrate and the sealing resin of the semiconductor apparatus, after the heating.
    Type: Application
    Filed: September 2, 2014
    Publication date: June 18, 2015
    Inventors: Takeshi WATANABE, Takashi IMOTO, Yuusuke TAKANO, Soichi HOMMA, Katsunori SHIBUYA
  • Publication number: 20150171056
    Abstract: In a manufacturing method of a semiconductor device of an embodiment, a plurality of semiconductor packages, as objects to be processed, each including a semiconductor chip mounted on a wiring board and a sealing resin layer, and a tray including a plurality of housing parts are prepared. The semiconductor packages are respectively disposed in the plurality of housing parts of the tray. A metal material is sputtered on the semiconductor packages disposed in the housing parts, to thereby form a conductive shield layer covering an upper surface and side surfaces of each of the sealing resin layers and at least a part of side surfaces of each of the wiring boards.
    Type: Application
    Filed: September 10, 2014
    Publication date: June 18, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yoshiaki Goto, Takashi Imoto, Takeshi Watanabe, Yuusuke Takano, Yusuke Akada, Yuji Karakane, Yoshinori Okayama, Akihiko Yanagida